[PARISC] Update sba_iommu from parisc tree
revert use of %%sr0 in fdc asm. Thanks to Joel Soete for pointing out this oversight. Signed-off-by: Grant Grundler <grundler@parisc-linux.org> 2.6.14-rc2-pa3 move "sync" outside the main loop that fills IO Pdir. Signed-off-by: Grant Grundler <grundler@parisc-linux.org> remove explicit use of sr0 in fdc ops. Thanks to Joel Soete for reminding me were I added those... Signed-off-by: Grant Grundler <grundler@parisc-linux.org> 2.6.14-rc2-pa2 - make SBA more anal about invalidating pdir entries Previous code cleared the valid flag a pdir entry but it did NOT guarantee this change was visible to the PDIR before writing the PCOM register. Ie the SBA could pick up a stale entry if the write happened to hit the SBA before the cacheline was flushed from the cache. Long term, I think I want to make this a compile time flag. Developement tree should enable anal pdir checking by default and Debian can disable it with either a CONFIG option or one-line patch. fdc/sync options can only negatively affect performance though I haven't measure how much yet. If someone can run netperf TCP_RR across gige and compare -pa1 and -pa2, that would be sufficient. Cleaned up the use of "fdc" to make sure it's using "kernel" space id (specify sr0 but maps to sr4-7). It seems a bit fragile to assume "sr1" gets loaded with KERNEL_SPACE which is how the code works today. Tested on 32 and 64-bit SMP kernels on j6k. Signed-off-by: Grant Grundler <grundler@parisc-linux.org> remove PDC_NARROW from SBA and document history of PDC_NARROW a bit. It will still show up in an older kernel's .config file. Signed-off-by: Grant Grundler <grundler@parisc-linux.org> if/ifdef cleanups from Joel Soete. Signed-off-by: Grant Grundler <grundler@parisc-linux.org> 2.6.12-rc4-pa2 fix 32-bit support for Astro platforms o Since my last SBA code change, SBA could allocate more than 1GB of IOVA space on Astro boxes with more than 1GB of RAM when running 32-bit kernel. This is bad since IOMMU can only talk to the first 1GB at most. Kudos to jejb for quickly spotting that bug. o jejb also noted SBA should *always* reject DMA masks > 32-bits since DMA-mapping.txt indicates caller should try again with 32-bits. o off-by-one error when comparing the mask to IOVA space size. Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>wifi-calibration
Grant Grundler
Kyle McMartin
parent
53f01bba49
commit
64908ad95c
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@ -91,8 +91,8 @@ extern struct proc_dir_entry * proc_mckinley_root;
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#define DBG_RES(x...)
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#endif
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#if defined(__LP64__) && !defined(CONFIG_PDC_NARROW)
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/* "low end" PA8800 machines use ZX1 chipset */
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#if defined(CONFIG_64BIT)
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/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
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#define ZX1_SUPPORT
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#endif
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@ -231,7 +231,7 @@ struct ioc {
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spinlock_t res_lock;
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unsigned int res_bitshift; /* from the LEFT! */
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unsigned int res_size; /* size of resource map in bytes */
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#if SBA_HINT_SUPPORT
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#ifdef SBA_HINT_SUPPORT
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/* FIXME : DMA HINTs not used */
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unsigned long hint_mask_pdir; /* bits used for DMA hints */
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unsigned int hint_shift_pdir;
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@ -294,7 +294,7 @@ static unsigned long piranha_bad_128k = 0;
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/* Looks nice and keeps the compiler happy */
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#define SBA_DEV(d) ((struct sba_device *) (d))
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#if SBA_AGP_SUPPORT
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#ifdef SBA_AGP_SUPPORT
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static int reserve_sba_gart = 1;
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#endif
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@ -314,7 +314,7 @@ static int reserve_sba_gart = 1;
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#define WRITE_REG32(val, addr) __raw_writel(cpu_to_le32(val), addr)
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#define WRITE_REG64(val, addr) __raw_writeq(cpu_to_le64(val), addr)
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#ifdef __LP64__
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#ifdef CONFIG_64BIT
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#define READ_REG(addr) READ_REG64(addr)
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#define WRITE_REG(value, addr) WRITE_REG64(value, addr)
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#else
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@ -324,7 +324,7 @@ static int reserve_sba_gart = 1;
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#ifdef DEBUG_SBA_INIT
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/* NOTE: When __LP64__ isn't defined, READ_REG64() is two 32-bit reads */
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/* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
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/**
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* sba_dump_ranges - debugging only - print ranges assigned to this IOA
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@ -364,7 +364,7 @@ static void sba_dump_tlb(void __iomem *hpa)
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#else
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#define sba_dump_ranges(x)
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#define sba_dump_tlb(x)
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#endif
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#endif /* DEBUG_SBA_INIT */
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#ifdef ASSERT_PDIR_SANITY
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@ -674,7 +674,7 @@ sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
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*
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***************************************************************/
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#if SBA_HINT_SUPPORT
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#ifdef SBA_HINT_SUPPORT
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#define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
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#endif
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@ -743,9 +743,8 @@ sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
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* (bit #61, big endian), we have to flush and sync every time
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* IO-PDIR is changed in Ike/Astro.
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*/
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if (ioc_needs_fdc) {
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asm volatile("fdc 0(%%sr1,%0)\n\tsync" : : "r" (pdir_ptr));
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}
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if (ioc_needs_fdc)
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asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
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}
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@ -769,42 +768,57 @@ static SBA_INLINE void
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sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
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{
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u32 iovp = (u32) SBA_IOVP(ioc,iova);
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/* Even though this is a big-endian machine, the entries
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** in the iopdir are little endian. That's why we clear the byte
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** at +7 instead of at +0.
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*/
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int off = PDIR_INDEX(iovp)*sizeof(u64)+7;
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u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
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#ifdef ASSERT_PDIR_SANITY
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/* Assert first pdir entry is set */
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if (0x80 != (((u8 *) ioc->pdir_base)[off])) {
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/* Assert first pdir entry is set.
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**
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** Even though this is a big-endian machine, the entries
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** in the iopdir are little endian. That's why we look at
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** the byte at +7 instead of at +0.
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*/
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if (0x80 != (((u8 *) pdir_ptr)[7])) {
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sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
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}
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#endif
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if (byte_cnt <= IOVP_SIZE)
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if (byte_cnt > IOVP_SIZE)
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{
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iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
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#if 0
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unsigned long entries_per_cacheline = ioc_needs_fdc ?
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L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
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- (unsigned long) pdir_ptr;
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: 262144;
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#endif
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/*
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** clear I/O PDIR entry "valid" bit
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** Do NOT clear the rest - save it for debugging.
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** We should only clear bits that have previously
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** been enabled.
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*/
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((u8 *)(ioc->pdir_base))[off] = 0;
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} else {
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u32 t = get_order(byte_cnt) + PAGE_SHIFT;
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/* set "size" field for PCOM */
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iovp |= get_order(byte_cnt) + PAGE_SHIFT;
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iovp |= t;
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do {
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/* clear I/O Pdir entry "valid" bit first */
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((u8 *)(ioc->pdir_base))[off] = 0;
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off += sizeof(u64);
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((u8 *) pdir_ptr)[7] = 0;
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if (ioc_needs_fdc) {
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asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
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#if 0
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entries_per_cacheline = L1_CACHE_SHIFT - 3;
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#endif
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}
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pdir_ptr++;
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byte_cnt -= IOVP_SIZE;
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} while (byte_cnt > 0);
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}
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} while (byte_cnt > IOVP_SIZE);
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} else
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iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
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/*
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** clear I/O PDIR entry "valid" bit.
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** We have to R/M/W the cacheline regardless how much of the
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** pdir entry that we clobber.
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** The rest of the entry would be useful for debugging if we
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** could dump core on HPMC.
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*/
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((u8 *) pdir_ptr)[7] = 0;
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if (ioc_needs_fdc)
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asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
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WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
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}
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@ -819,18 +833,29 @@ sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
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static int sba_dma_supported( struct device *dev, u64 mask)
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{
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struct ioc *ioc;
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if (dev == NULL) {
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printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
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BUG();
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return(0);
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}
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/* Documentation/DMA-mapping.txt tells drivers to try 64-bit first,
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* then fall back to 32-bit if that fails.
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* We are just "encouraging" 32-bit DMA masks here since we can
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* never allow IOMMU bypass unless we add special support for ZX1.
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*/
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if (mask > ~0U)
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return 0;
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ioc = GET_IOC(dev);
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/* check if mask is > than the largest IO Virt Address */
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return((int) (mask >= (ioc->ibase +
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(ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
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/*
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* check if mask is >= than the current max IO Virt Address
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* The max IO Virt address will *always* < 30 bits.
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*/
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return((int)(mask >= (ioc->ibase - 1 +
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(ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
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}
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@ -898,11 +923,17 @@ sba_map_single(struct device *dev, void *addr, size_t size,
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size -= IOVP_SIZE;
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pdir_start++;
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}
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/* form complete address */
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/* force FDC ops in io_pdir_entry() to be visible to IOMMU */
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if (ioc_needs_fdc)
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asm volatile("sync" : : );
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#ifdef ASSERT_PDIR_SANITY
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sba_check_pdir(ioc,"Check after sba_map_single()");
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#endif
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spin_unlock_irqrestore(&ioc->res_lock, flags);
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/* form complete address */
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return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
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}
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@ -958,12 +989,19 @@ sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
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d--;
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}
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ioc->saved_cnt = 0;
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READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
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}
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#else /* DELAYED_RESOURCE_CNT == 0 */
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sba_free_range(ioc, iova, size);
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/* If fdc's were issued, force fdc's to be visible now */
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if (ioc_needs_fdc)
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asm volatile("sync" : : );
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READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
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#endif /* DELAYED_RESOURCE_CNT == 0 */
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spin_unlock_irqrestore(&ioc->res_lock, flags);
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/* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
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@ -1106,6 +1144,10 @@ sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
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*/
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filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
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/* force FDC ops in io_pdir_entry() to be visible to IOMMU */
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if (ioc_needs_fdc)
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asm volatile("sync" : : );
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#ifdef ASSERT_PDIR_SANITY
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if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
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{
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@ -1234,8 +1276,10 @@ sba_alloc_pdir(unsigned int pdir_size)
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unsigned long pdir_order = get_order(pdir_size);
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pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
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if (NULL == (void *) pdir_base)
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panic("sba_ioc_init() could not allocate I/O Page Table\n");
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if (NULL == (void *) pdir_base) {
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panic("%s() could not allocate I/O Page Table\n",
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__FUNCTION__);
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}
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/* If this is not PA8700 (PCX-W2)
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** OR newer than ver 2.2
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@ -1353,7 +1397,7 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
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u32 iova_space_mask;
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u32 iova_space_size;
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int iov_order, tcnfg;
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#if SBA_AGP_SUPPORT
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#ifdef SBA_AGP_SUPPORT
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int agp_found = 0;
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#endif
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/*
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@ -1390,7 +1434,7 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
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DBG_INIT("%s() pdir %p size %x\n",
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__FUNCTION__, ioc->pdir_base, ioc->pdir_size);
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#if SBA_HINT_SUPPORT
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#ifdef SBA_HINT_SUPPORT
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ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
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ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
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@ -1414,7 +1458,7 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
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WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
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#ifdef __LP64__
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#ifdef CONFIG_64BIT
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/*
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** Setting the upper bits makes checking for bypass addresses
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** a little faster later on.
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@ -1447,7 +1491,7 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
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*/
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WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
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#if SBA_AGP_SUPPORT
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#ifdef SBA_AGP_SUPPORT
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/*
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** If an AGP device is present, only use half of the IOV space
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** for PCI DMA. Unfortunately we can't know ahead of time
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@ -1499,11 +1543,9 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
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if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
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iova_space_size = 1 << (20 - PAGE_SHIFT);
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}
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#ifdef __LP64__
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else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
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iova_space_size = 1 << (30 - PAGE_SHIFT);
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}
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#endif
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/*
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** iova space must be log2() in size.
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@ -1529,7 +1571,7 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
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DBG_INIT("%s() pdir %p size %x\n",
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__FUNCTION__, ioc->pdir_base, pdir_size);
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#if SBA_HINT_SUPPORT
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#ifdef SBA_HINT_SUPPORT
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/* FIXME : DMA HINTs not used */
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ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
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ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
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