MIPS: OCTEON: irq: add CIB and other fixes
- Use of_irq_init() to initialize interrupt controllers - Get rid of some unlikely() - Add CIB to support SATA and other interrupts - Add support for CIU SUM2 interrupt sources Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Leonid Rosenboim <lrosenboim@caviumnetworks.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Signed-off-by: Peter Swain <peter.swain@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8947/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Documentation/devicetree/bindings/mips/cavium/cib.txt
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Documentation/devicetree/bindings/mips/cavium/cib.txt
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* Cavium Interrupt Bus widget
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Properties:
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- compatible: "cavium,octeon-7130-cib"
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Compatibility with cn70XX SoCs.
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- interrupt-controller: This is an interrupt controller.
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- reg: Two elements consisting of the addresses of the RAW and EN
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registers of the CIB block
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- cavium,max-bits: The index (zero based) of the highest numbered bit
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in the CIB block.
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- interrupt-parent: Always the CIU on the SoC.
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- interrupts: The CIU line to which the CIB block is connected.
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- #interrupt-cells: Must be <2>. The first cell is the bit within the
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CIB. The second cell specifies the triggering semantics of the
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line.
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Example:
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interrupt-controller@107000000e000 {
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compatible = "cavium,octeon-7130-cib";
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reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */
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<0x10700 0x0000e100 0x0 0x8>; /* EN */
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cavium,max-bits = <23>;
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interrupt-controller;
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interrupt-parent = <&ciu>;
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interrupts = <1 24>;
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/* Interrupts are specified by two parts:
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* 1) Bit number in the CIB* registers
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* 2) Triggering (1 - edge rising
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* 2 - edge falling
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* 4 - level active high
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* 8 - level active low)
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*/
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#interrupt-cells = <2>;
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};
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