intel-iommu: Fix integer wrap on 32 bit kernels
The following 64 bit promotions are necessary to handle memory above the 4GiB boundary correctly. [dwmw2: Fix the second part not to need 64-bit arithmetic at all] Signed-off-by: Benjamin LaHaise <ben.lahaise@neterion.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -735,7 +735,7 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
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return NULL;
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domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
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pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
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pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
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if (cmpxchg64(&pte->val, 0ULL, pteval)) {
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/* Someone else set it while we were thinking; use theirs. */
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free_pgtable_page(tmp_page);
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@ -2648,10 +2648,9 @@ static void flush_unmaps(void)
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unsigned long mask;
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struct iova *iova = deferred_flush[i].iova[j];
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mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
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mask = ilog2(mask >> VTD_PAGE_SHIFT);
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mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
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iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
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iova->pfn_lo << PAGE_SHIFT, mask);
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(uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
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__free_iova(&deferred_flush[i].domain[j]->iovad, iova);
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}
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deferred_flush[i].next = 0;
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