From 0a26344440b5f9940c99112fdc3804f073b1f5a7 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 25 Jul 2014 06:11:15 -0600 Subject: [PATCH 1/6] ARM: OMAP2+: clock: allow omap2_dpll_round_rate() to round to next-lowest rate Change the behavior of omap2_dpll_round_rate() to round to either the exact rate requested, or the next lowest rate that the clock is able to provide. This is not an ideal fix, but is intended to provide a relatively safe way for drivers to set PLL rates, until a better solution can be implemented. For the time being, omap3_noncore_dpll_set_rate() is still allowed to set its rate to something other than what the caller requested; but will warn when this occurs. Cc: Tomi Valkeinen Cc: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clkt_dpll.c | 28 +++++++++++++++++++++------- arch/arm/mach-omap2/dpll3xxx.c | 13 +++++++++++-- 2 files changed, 32 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 332af927f4d3..85701142c5fc 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -293,10 +293,13 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, { struct clk_hw_omap *clk = to_clk_hw_omap(hw); int m, n, r, scaled_max_m; + int min_delta_m = INT_MAX, min_delta_n = INT_MAX; unsigned long scaled_rt_rp; unsigned long new_rate = 0; struct dpll_data *dd; unsigned long ref_rate; + long delta; + long prev_min_delta = LONG_MAX; const char *clk_name; if (!clk || !clk->dpll_data) @@ -342,23 +345,34 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, if (r == DPLL_MULT_UNDERFLOW) continue; + /* skip rates above our target rate */ + delta = target_rate - new_rate; + if (delta < 0) + continue; + + if (delta < prev_min_delta) { + prev_min_delta = delta; + min_delta_m = m; + min_delta_n = n; + } + pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n", clk_name, m, n, new_rate); - if (target_rate == new_rate) { - dd->last_rounded_m = m; - dd->last_rounded_n = n; - dd->last_rounded_rate = target_rate; + if (delta == 0) break; - } } - if (target_rate != new_rate) { + if (prev_min_delta == LONG_MAX) { pr_debug("clock: %s: cannot round to rate %lu\n", clk_name, target_rate); return ~0; } - return target_rate; + dd->last_rounded_m = min_delta_m; + dd->last_rounded_n = min_delta_n; + dd->last_rounded_rate = target_rate - prev_min_delta; + + return dd->last_rounded_rate; } diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 6d7ba37e2257..b6860bfb05b3 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -478,6 +478,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_hw_omap *clk = to_clk_hw_omap(hw); struct clk *new_parent = NULL; + unsigned long rrate; u16 freqsel = 0; struct dpll_data *dd; int ret; @@ -505,8 +506,16 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, __clk_prepare(dd->clk_ref); clk_enable(dd->clk_ref); - if (dd->last_rounded_rate != rate) - rate = __clk_round_rate(hw->clk, rate); + /* XXX this check is probably pointless in the CCF context */ + if (dd->last_rounded_rate != rate) { + rrate = __clk_round_rate(hw->clk, rate); + if (rrate != rate) { + pr_warn("%s: %s: final rate %lu does not match desired rate %lu\n", + __func__, __clk_get_name(hw->clk), + rrate, rate); + rate = rrate; + } + } if (dd->last_rounded_rate == 0) return -EINVAL; From 9b5f7428f8b16bd8980213f2b70baf1dd0b9e36c Mon Sep 17 00:00:00 2001 From: Jeremy Vial Date: Thu, 31 Jul 2014 15:10:33 +0200 Subject: [PATCH 2/6] ARM: OMAP3: Fix choice of omap3_restore_es function in OMAP34XX rev3.1.2 case. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the comment “restore_es3: applies to 34xx >= ES3.0" in "arch/arm/mach-omap2/sleep34xx.S”, omap3_restore_es3 should be used if the revision of an OMAP34xx is ES3.1.2. Signed-off-by: Jeremy Vial Cc: stable@vger.kernel.org Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/control.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index f4796c002070..e84e3b4bfde1 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -309,7 +309,8 @@ void omap3_save_scratchpad_contents(void) scratchpad_contents.public_restore_ptr = virt_to_phys(omap3_restore_3630); else if (omap_rev() != OMAP3430_REV_ES3_0 && - omap_rev() != OMAP3430_REV_ES3_1) + omap_rev() != OMAP3430_REV_ES3_1 && + omap_rev() != OMAP3430_REV_ES3_1_2) scratchpad_contents.public_restore_ptr = virt_to_phys(omap3_restore); else From ae21e6180a03c147514c606b4e649690e0cbd40e Mon Sep 17 00:00:00 2001 From: Jeremy Vial Date: Thu, 31 Jul 2014 15:10:34 +0200 Subject: [PATCH 3/6] ARM: OMAP3: Fix coding style problems in arch/arm/mach-omap2/control.c Fix coding style problems in arch/arm/mach-omap2/control.c. Signed-off-by: Jeremy Vial Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/control.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index e84e3b4bfde1..da041b4ab29c 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -280,6 +280,7 @@ void omap3_clear_scratchpad_contents(void) u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; void __iomem *v_addr; u32 offset = 0; + v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); if (omap3xxx_prm_clear_global_cold_reset()) { for ( ; offset <= max_offset; offset += 0x4) @@ -464,7 +465,6 @@ void omap3_control_save_context(void) control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); control_context.padconf_sys_nirq = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); - return; } void omap3_control_restore_context(void) @@ -522,7 +522,6 @@ void omap3_control_restore_context(void) omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); omap_ctrl_writel(control_context.padconf_sys_nirq, OMAP343X_CONTROL_PADCONF_SYSNIRQ); - return; } void omap3630_ctrl_disable_rta(void) From c9c32c5049b8a36919968dbfdf08bbeda0c5e381 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Thu, 7 Aug 2014 17:44:19 +0200 Subject: [PATCH 4/6] ARM: dts: Fix the sort ordering of EHCI and HSIC in rk3288.dtsi The EHCI and HSIC device tree nodes were added in the wrong place. Fix them. Signed-off-by: Doug Anderson Signed-off-by: Kever Yang Signed-off-by: Heiko Stuebner Signed-off-by: Olof Johansson --- arch/arm/boot/dts/rk3288.dtsi | 40 +++++++++++++++++------------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index e7cb00873dd4..5950b0a53224 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -195,6 +195,26 @@ status = "disabled"; }; + usb_host0_ehci: usb@ff500000 { + compatible = "generic-ehci"; + reg = <0xff500000 0x100>; + interrupts = ; + clocks = <&cru HCLK_USBHOST0>; + clock-names = "usbhost"; + status = "disabled"; + }; + + /* NOTE: ohci@ff520000 doesn't actually work on hardware */ + + usb_hsic: usb@ff5c0000 { + compatible = "generic-ehci"; + reg = <0xff5c0000 0x100>; + interrupts = ; + clocks = <&cru HCLK_HSIC>; + clock-names = "usbhost"; + status = "disabled"; + }; + i2c0: i2c@ff650000 { compatible = "rockchip,rk3288-i2c"; reg = <0xff650000 0x1000>; @@ -251,26 +271,6 @@ status = "disabled"; }; - usb_host0_ehci: usb@ff500000 { - compatible = "generic-ehci"; - reg = <0xff500000 0x100>; - interrupts = ; - clocks = <&cru HCLK_USBHOST0>; - clock-names = "usbhost"; - status = "disabled"; - }; - - /* NOTE: ohci@ff520000 doesn't actually work on hardware */ - - usb_hsic: usb@ff5c0000 { - compatible = "generic-ehci"; - reg = <0xff5c0000 0x100>; - interrupts = ; - clocks = <&cru HCLK_HSIC>; - clock-names = "usbhost"; - status = "disabled"; - }; - gic: interrupt-controller@ffc01000 { compatible = "arm,gic-400"; interrupt-controller; From 01601b349582caa617618b5fa7d9b08bd328626a Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Tue, 5 Aug 2014 14:43:10 +0200 Subject: [PATCH 5/6] ARM: EXYNOS: Fix suspend/resume sequences Due to recent consolidation of Exynos suspend and cpuidle code, some parts of suspend and resume sequences are executed two times, once from exynos_pm_syscore_ops and then from exynos_cpu_pm_notifier() and thus it breaks suspend, at least on Exynos4-based boards. In addition, simple core power down from a cpuidle driver could, in case of CPU 0 could result in calling functions that are specific to suspend and deeper idle states. This patch fixes the issue by moving those operations outside the CPU PM notifier into suspend and AFTR code paths. This leads to a bit of code duplication, but allows additional code simplification, so in the end more code is removed than added. Fixes: 85f9f90808b4 ("ARM: EXYNOS: Use the cpu_pm notifier for pm") Cc: Kukjin Kim Cc: Arnd Bergmann Cc: Olof Johansson Cc: arm@kernel.org Signed-off-by: Tomasz Figa [b.zolnierkie: ported patch over current changes] [b.zolnierkie: fixed exynos_aftr_finisher() return value] Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: Olof Johansson --- arch/arm/mach-exynos/pm.c | 163 ++++++++++++++----------------- drivers/cpuidle/cpuidle-exynos.c | 25 +---- 2 files changed, 80 insertions(+), 108 deletions(-) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 18646b7e226b..abefacb45976 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -114,26 +114,6 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) #define S5P_CHECK_AFTR 0xFCBA0D10 #define S5P_CHECK_SLEEP 0x00000BAD -/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ -static void exynos_set_wakeupmask(long mask) -{ - pmu_raw_writel(mask, S5P_WAKEUP_MASK); -} - -static void exynos_cpu_set_boot_vector(long flags) -{ - __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR); - __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG); -} - -void exynos_enter_aftr(void) -{ - exynos_set_wakeupmask(0x0000ff3e); - exynos_cpu_set_boot_vector(S5P_CHECK_AFTR); - /* Set value of power down register for aftr mode */ - exynos_sys_powerdown_conf(SYS_AFTR); -} - /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; @@ -173,6 +153,82 @@ static void exynos_cpu_restore_register(void) : "cc"); } +static void exynos_pm_central_suspend(void) +{ + unsigned long tmp; + + /* Setting Central Sequence Register for power down mode */ + tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); + tmp &= ~S5P_CENTRAL_LOWPWR_CFG; + pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); +} + +static int exynos_pm_central_resume(void) +{ + unsigned long tmp; + + /* + * If PMU failed while entering sleep mode, WFI will be + * ignored by PMU and then exiting cpu_do_idle(). + * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically + * in this situation. + */ + tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); + if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { + tmp |= S5P_CENTRAL_LOWPWR_CFG; + pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); + /* clear the wakeup state register */ + pmu_raw_writel(0x0, S5P_WAKEUP_STAT); + /* No need to perform below restore code */ + return -1; + } + + return 0; +} + +/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ +static void exynos_set_wakeupmask(long mask) +{ + pmu_raw_writel(mask, S5P_WAKEUP_MASK); +} + +static void exynos_cpu_set_boot_vector(long flags) +{ + __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR); + __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG); +} + +static int exynos_aftr_finisher(unsigned long flags) +{ + exynos_set_wakeupmask(0x0000ff3e); + exynos_cpu_set_boot_vector(S5P_CHECK_AFTR); + /* Set value of power down register for aftr mode */ + exynos_sys_powerdown_conf(SYS_AFTR); + cpu_do_idle(); + + return 1; +} + +void exynos_enter_aftr(void) +{ + cpu_pm_enter(); + + exynos_pm_central_suspend(); + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) + exynos_cpu_save_register(); + + cpu_suspend(0, exynos_aftr_finisher); + + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { + scu_enable(S5P_VA_SCU); + exynos_cpu_restore_register(); + } + + exynos_pm_central_resume(); + + cpu_pm_exit(); +} + static int exynos_cpu_suspend(unsigned long arg) { #ifdef CONFIG_CACHE_L2X0 @@ -217,16 +273,6 @@ static void exynos_pm_prepare(void) pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0); } -static void exynos_pm_central_suspend(void) -{ - unsigned long tmp; - - /* Setting Central Sequence Register for power down mode */ - tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); - tmp &= ~S5P_CENTRAL_LOWPWR_CFG; - pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); -} - static int exynos_pm_suspend(void) { unsigned long tmp; @@ -244,29 +290,6 @@ static int exynos_pm_suspend(void) return 0; } -static int exynos_pm_central_resume(void) -{ - unsigned long tmp; - - /* - * If PMU failed while entering sleep mode, WFI will be - * ignored by PMU and then exiting cpu_do_idle(). - * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically - * in this situation. - */ - tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); - if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { - tmp |= S5P_CENTRAL_LOWPWR_CFG; - pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); - /* clear the wakeup state register */ - pmu_raw_writel(0x0, S5P_WAKEUP_STAT); - /* No need to perform below restore code */ - return -1; - } - - return 0; -} - static void exynos_pm_resume(void) { if (exynos_pm_central_resume()) @@ -369,44 +392,10 @@ static const struct platform_suspend_ops exynos_suspend_ops = { .valid = suspend_valid_only_mem, }; -static int exynos_cpu_pm_notifier(struct notifier_block *self, - unsigned long cmd, void *v) -{ - int cpu = smp_processor_id(); - - switch (cmd) { - case CPU_PM_ENTER: - if (cpu == 0) { - exynos_pm_central_suspend(); - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) - exynos_cpu_save_register(); - } - break; - - case CPU_PM_EXIT: - if (cpu == 0) { - if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { - scu_enable(S5P_VA_SCU); - exynos_cpu_restore_register(); - } - exynos_pm_central_resume(); - } - break; - } - - return NOTIFY_OK; -} - -static struct notifier_block exynos_cpu_pm_notifier_block = { - .notifier_call = exynos_cpu_pm_notifier, -}; - void __init exynos_pm_init(void) { u32 tmp; - cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block); - /* Platform-specific GIC callback */ gic_arch_extn.irq_set_wake = exynos_irq_set_wake; diff --git a/drivers/cpuidle/cpuidle-exynos.c b/drivers/cpuidle/cpuidle-exynos.c index 7c0151263828..ba9b34b579f3 100644 --- a/drivers/cpuidle/cpuidle-exynos.c +++ b/drivers/cpuidle/cpuidle-exynos.c @@ -20,25 +20,6 @@ static void (*exynos_enter_aftr)(void); -static int idle_finisher(unsigned long flags) -{ - exynos_enter_aftr(); - cpu_do_idle(); - - return 1; -} - -static int exynos_enter_core0_aftr(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index) -{ - cpu_pm_enter(); - cpu_suspend(0, idle_finisher); - cpu_pm_exit(); - - return index; -} - static int exynos_enter_lowpower(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) @@ -51,8 +32,10 @@ static int exynos_enter_lowpower(struct cpuidle_device *dev, if (new_index == 0) return arm_cpuidle_simple_enter(dev, drv, new_index); - else - return exynos_enter_core0_aftr(dev, drv, new_index); + + exynos_enter_aftr(); + + return new_index; } static struct cpuidle_driver exynos_idle_driver = { From ee34fb97a96ceac3334705ebab8b541ca291699f Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Sat, 9 Aug 2014 08:25:50 -0700 Subject: [PATCH 6/6] ARM: dts: exynos5420: remove disp_pd This was caused by commit 5a8da524049c ("ARM: dts: exynos5420: add dsi node"), which conflicted with d51cad7df871 ("ARM: dts: remove display power domain for exynos5420"). The DTS addition should never have been merged through the DRM tree in the first place, and it lacked an ack from the platform maintainer (who would have known that the disp_pd reference got removed). Signed-off-by: Stephen Rothwell Signed-off-by: Olof Johansson --- arch/arm/boot/dts/exynos5420.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 95ec37dff3e8..bfe056d9148c 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -525,7 +525,6 @@ compatible = "samsung,exynos5410-mipi-dsi"; reg = <0x14500000 0x10000>; interrupts = <0 82 0>; - samsung,power-domain = <&disp_pd>; phys = <&mipi_phy 1>; phy-names = "dsim"; clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;