Merge branch 'rmobile/core' into rmobile-fixes-for-linus
This commit is contained in:
commit
65670a1b75
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@ -116,4 +116,6 @@ endmenu
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config SH_CLK_CPG
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bool
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source "drivers/sh/Kconfig"
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endif
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@ -565,12 +565,50 @@ static struct platform_device *qhd_devices[] __initdata = {
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/* FSI */
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#define IRQ_FSI evt2irq(0x1840)
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static int fsi_set_rate(int is_porta, int rate)
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{
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struct clk *fsib_clk;
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struct clk *fdiv_clk = &sh7372_fsidivb_clk;
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int ret;
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/* set_rate is not needed if port A */
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if (is_porta)
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return 0;
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fsib_clk = clk_get(NULL, "fsib_clk");
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if (IS_ERR(fsib_clk))
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return -EINVAL;
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switch (rate) {
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case 48000:
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clk_set_rate(fsib_clk, clk_round_rate(fsib_clk, 85428000));
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clk_set_rate(fdiv_clk, clk_round_rate(fdiv_clk, 12204000));
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ret = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
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break;
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default:
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pr_err("unsupported rate in FSI2 port B\n");
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ret = -EINVAL;
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break;
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}
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clk_put(fsib_clk);
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return ret;
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}
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static struct sh_fsi_platform_info fsi_info = {
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.porta_flags = SH_FSI_BRS_INV |
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SH_FSI_OUT_SLAVE_MODE |
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SH_FSI_IN_SLAVE_MODE |
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SH_FSI_OFMT(PCM) |
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SH_FSI_IFMT(PCM),
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.portb_flags = SH_FSI_BRS_INV |
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SH_FSI_BRM_INV |
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SH_FSI_LRS_INV |
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SH_FSI_OFMT(SPDIF),
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.set_rate = fsi_set_rate,
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};
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static struct resource fsi_resources[] = {
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@ -634,6 +672,7 @@ static struct platform_device lcdc1_device = {
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static struct sh_mobile_hdmi_info hdmi_info = {
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.lcd_chan = &sh_mobile_lcdc1_info.ch[0],
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.lcd_dev = &lcdc1_device.dev,
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.flags = HDMI_SND_SRC_SPDIF,
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};
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static struct resource hdmi_resources[] = {
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@ -992,6 +1031,7 @@ static void __init ap4evb_map_io(void)
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#define GPIO_PORT9CR 0xE6051009
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#define GPIO_PORT10CR 0xE605100A
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#define USCCR1 0xE6058144
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static void __init ap4evb_init(void)
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{
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u32 srcr4;
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@ -1062,7 +1102,7 @@ static void __init ap4evb_init(void)
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/* setup USB phy */
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__raw_writew(0x8a0a, 0xE6058130); /* USBCR2 */
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/* enable FSI2 */
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/* enable FSI2 port A (ak4643) */
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gpio_request(GPIO_FN_FSIAIBT, NULL);
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gpio_request(GPIO_FN_FSIAILR, NULL);
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gpio_request(GPIO_FN_FSIAISLD, NULL);
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@ -1079,6 +1119,10 @@ static void __init ap4evb_init(void)
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gpio_request(GPIO_PORT41, NULL);
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gpio_direction_input(GPIO_PORT41);
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/* setup FSI2 port B (HDMI) */
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gpio_request(GPIO_FN_FSIBCK, NULL);
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__raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
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/* set SPU2 clock to 119.6 MHz */
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clk = clk_get(NULL, "spu_clk");
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if (!IS_ERR(clk)) {
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@ -50,6 +50,9 @@
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR4 0xe6150140
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#define FSIDIVA 0xFE1F8000
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#define FSIDIVB 0xFE1F8008
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/* Platforms must set frequency on their DV_CLKI pin */
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struct clk sh7372_dv_clki_clk = {
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};
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@ -288,6 +291,7 @@ struct clk sh7372_pllc2_clk = {
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.ops = &pllc2_clk_ops,
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.parent = &extal1_div2_clk,
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.freq_table = pllc2_freq_table,
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.nr_freqs = ARRAY_SIZE(pllc2_freq_table) - 1,
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.parent_table = pllc2_parent,
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.parent_num = ARRAY_SIZE(pllc2_parent),
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};
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@ -417,6 +421,101 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
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fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
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};
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/* FSI DIV */
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static unsigned long fsidiv_recalc(struct clk *clk)
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{
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unsigned long value;
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value = __raw_readl(clk->mapping->base);
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if ((value & 0x3) != 0x3)
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return 0;
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value >>= 16;
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if (value < 2)
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return 0;
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return clk->parent->rate / value;
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}
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static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk_rate_div_range_round(clk, 2, 0xffff, rate);
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}
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static void fsidiv_disable(struct clk *clk)
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{
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__raw_writel(0, clk->mapping->base);
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}
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static int fsidiv_enable(struct clk *clk)
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{
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unsigned long value;
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value = __raw_readl(clk->mapping->base) >> 16;
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if (value < 2) {
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fsidiv_disable(clk);
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return -ENOENT;
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}
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__raw_writel((value << 16) | 0x3, clk->mapping->base);
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return 0;
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}
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static int fsidiv_set_rate(struct clk *clk,
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unsigned long rate, int algo_id)
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{
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int idx;
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if (clk->parent->rate == rate) {
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fsidiv_disable(clk);
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return 0;
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}
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idx = (clk->parent->rate / rate) & 0xffff;
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if (idx < 2)
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return -ENOENT;
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__raw_writel(idx << 16, clk->mapping->base);
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return fsidiv_enable(clk);
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}
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static struct clk_ops fsidiv_clk_ops = {
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.recalc = fsidiv_recalc,
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.round_rate = fsidiv_round_rate,
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.set_rate = fsidiv_set_rate,
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.enable = fsidiv_enable,
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.disable = fsidiv_disable,
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};
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static struct clk_mapping sh7372_fsidiva_clk_mapping = {
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.phys = FSIDIVA,
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.len = 8,
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};
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struct clk sh7372_fsidiva_clk = {
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.ops = &fsidiv_clk_ops,
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.parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
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.mapping = &sh7372_fsidiva_clk_mapping,
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};
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static struct clk_mapping sh7372_fsidivb_clk_mapping = {
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.phys = FSIDIVB,
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.len = 8,
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};
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struct clk sh7372_fsidivb_clk = {
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.ops = &fsidiv_clk_ops,
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.parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
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.mapping = &sh7372_fsidivb_clk_mapping,
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};
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static struct clk *late_main_clks[] = {
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&sh7372_fsidiva_clk,
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&sh7372_fsidivb_clk,
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};
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enum { MSTP001,
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MSTP131, MSTP130,
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MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
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@ -585,6 +684,9 @@ void __init sh7372_clock_init(void)
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if (!ret)
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ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
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for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
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ret = clk_register(late_main_clks[k]);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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@ -35,12 +35,12 @@ static inline int gpio_cansleep(unsigned gpio)
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static inline int gpio_to_irq(unsigned gpio)
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{
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return -ENOSYS;
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return __gpio_to_irq(gpio);
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}
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static inline int irq_to_gpio(unsigned int irq)
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{
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return -EINVAL;
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return -ENOSYS;
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}
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#endif /* CONFIG_GPIOLIB */
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@ -464,5 +464,7 @@ extern struct clk sh7372_dv_clki_div2_clk;
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extern struct clk sh7372_pllc2_clk;
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extern struct clk sh7372_fsiack_clk;
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extern struct clk sh7372_fsibck_clk;
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extern struct clk sh7372_fsidiva_clk;
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extern struct clk sh7372_fsidivb_clk;
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#endif /* __ASM_SH7372_H__ */
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@ -616,13 +616,9 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
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/* get hold of clock */
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p->clk = clk_get(&p->pdev->dev, "cmt_fck");
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if (IS_ERR(p->clk)) {
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dev_warn(&p->pdev->dev, "using deprecated clock lookup\n");
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p->clk = clk_get(&p->pdev->dev, cfg->clk);
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if (IS_ERR(p->clk)) {
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dev_err(&p->pdev->dev, "cannot get clock\n");
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ret = PTR_ERR(p->clk);
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goto err1;
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}
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dev_err(&p->pdev->dev, "cannot get clock\n");
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ret = PTR_ERR(p->clk);
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goto err1;
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}
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if (resource_size(res) == 6) {
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@ -287,13 +287,9 @@ static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
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/* get hold of clock */
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p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
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if (IS_ERR(p->clk)) {
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dev_warn(&p->pdev->dev, "using deprecated clock lookup\n");
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p->clk = clk_get(&p->pdev->dev, cfg->clk);
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if (IS_ERR(p->clk)) {
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dev_err(&p->pdev->dev, "cannot get clock\n");
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ret = PTR_ERR(p->clk);
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goto err1;
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}
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dev_err(&p->pdev->dev, "cannot get clock\n");
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ret = PTR_ERR(p->clk);
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goto err1;
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}
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return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
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@ -393,13 +393,9 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
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/* get hold of clock */
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p->clk = clk_get(&p->pdev->dev, "tmu_fck");
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if (IS_ERR(p->clk)) {
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dev_warn(&p->pdev->dev, "using deprecated clock lookup\n");
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p->clk = clk_get(&p->pdev->dev, cfg->clk);
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if (IS_ERR(p->clk)) {
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dev_err(&p->pdev->dev, "cannot get clock\n");
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ret = PTR_ERR(p->clk);
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goto err1;
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}
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dev_err(&p->pdev->dev, "cannot get clock\n");
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ret = PTR_ERR(p->clk);
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goto err1;
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}
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return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
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@ -59,19 +59,19 @@ struct sh_mmcif_plat_data {
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#define MMCIF_CE_HOST_STS2 0x0000004C
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#define MMCIF_CE_VERSION 0x0000007C
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extern inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
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static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
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{
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return readl(addr + reg);
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}
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extern inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
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static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
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{
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writel(val, addr + reg);
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}
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#define SH_MMCIF_BBS 512 /* boot block size */
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extern inline void sh_mmcif_boot_cmd_send(void __iomem *base,
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static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
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unsigned long cmd, unsigned long arg)
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{
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sh_mmcif_writel(base, MMCIF_CE_INT, 0);
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@ -79,7 +79,7 @@ extern inline void sh_mmcif_boot_cmd_send(void __iomem *base,
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sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
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}
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extern inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
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static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
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{
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unsigned long tmp;
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int cnt;
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@ -95,14 +95,14 @@ extern inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
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return -1;
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}
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extern inline int sh_mmcif_boot_cmd(void __iomem *base,
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static inline int sh_mmcif_boot_cmd(void __iomem *base,
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unsigned long cmd, unsigned long arg)
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{
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sh_mmcif_boot_cmd_send(base, cmd, arg);
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return sh_mmcif_boot_cmd_poll(base, 0x00010000);
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}
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extern inline int sh_mmcif_boot_do_read_single(void __iomem *base,
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static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
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unsigned int block_nr,
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unsigned long *buf)
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{
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|
@ -125,7 +125,7 @@ extern inline int sh_mmcif_boot_do_read_single(void __iomem *base,
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return 0;
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}
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extern inline int sh_mmcif_boot_do_read(void __iomem *base,
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static inline int sh_mmcif_boot_do_read(void __iomem *base,
|
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unsigned long first_block,
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unsigned long nr_blocks,
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void *buf)
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|
@ -143,7 +143,7 @@ extern inline int sh_mmcif_boot_do_read(void __iomem *base,
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return ret;
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}
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|
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extern inline void sh_mmcif_boot_init(void __iomem *base)
|
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static inline void sh_mmcif_boot_init(void __iomem *base)
|
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{
|
||||
unsigned long tmp;
|
||||
|
||||
|
@ -177,7 +177,7 @@ extern inline void sh_mmcif_boot_init(void __iomem *base)
|
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sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
|
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}
|
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|
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extern inline void sh_mmcif_boot_slurp(void __iomem *base,
|
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static inline void sh_mmcif_boot_slurp(void __iomem *base,
|
||||
unsigned char *buf,
|
||||
unsigned long no_bytes)
|
||||
{
|
||||
|
|
|
@ -5,7 +5,6 @@ struct sh_timer_config {
|
|||
char *name;
|
||||
long channel_offset;
|
||||
int timer_bit;
|
||||
char *clk;
|
||||
unsigned long clockevent_rating;
|
||||
unsigned long clocksource_rating;
|
||||
};
|
||||
|
|
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Reference in a new issue