MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions
Detect if the core supports unique exception codes for the Read-Inhibit and Execute-Inhibit exceptions and set the option accordingly. The RI/XI exception support is detected by setting the 27th bit (IEC) of the PageGrain C0 register and reading back the value of that register to verify the bit is enabled. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7340/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -265,6 +265,7 @@
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#define PG_XIE (_ULCAST_(1) << 30)
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#define PG_ELPA (_ULCAST_(1) << 29)
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#define PG_ESP (_ULCAST_(1) << 28)
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#define PG_IEC (_ULCAST_(1) << 27)
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/*
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* R4x00 interrupt enable / cause bits
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@ -438,6 +438,15 @@ static void decode_configs(struct cpuinfo_mips *c)
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mips_probe_watch_registers(c);
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if (cpu_has_rixi) {
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/* Enable the RIXI exceptions */
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write_c0_pagegrain(read_c0_pagegrain() | PG_IEC);
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back_to_back_c0_hazard();
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/* Verify the IEC bit is set */
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if (read_c0_pagegrain() & PG_IEC)
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c->options |= MIPS_CPU_RIXIEX;
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}
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#ifndef CONFIG_MIPS_CPS
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if (cpu_has_mips_r2) {
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c->core = get_ebase_cpunum();
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