drm/i915/cnl: Cannonlake color init.
Cannonlake has same color setup as Geminilake. Legacy color load luts doesn't work anymore on Cannonlake+. Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1499374873-2454-1-git-send-email-rodrigo.vivi@intel.com
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@ -449,6 +449,7 @@ static const struct intel_device_info intel_cannonlake_info = {
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.gen = 10,
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.ddb_size = 1024,
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.has_csr = 1,
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.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
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};
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/*
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@ -615,7 +615,7 @@ void intel_color_init(struct drm_crtc *crtc)
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IS_BROXTON(dev_priv)) {
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dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
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dev_priv->display.load_luts = broadwell_load_luts;
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} else if (IS_GEMINILAKE(dev_priv)) {
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} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
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dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
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dev_priv->display.load_luts = glk_load_luts;
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} else {
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@ -3311,7 +3311,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
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plane_ctl = PLANE_CTL_ENABLE;
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if (!IS_GEMINILAKE(dev_priv)) {
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if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
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plane_ctl |=
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PLANE_CTL_PIPE_GAMMA_ENABLE |
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PLANE_CTL_PIPE_CSC_ENABLE |
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@ -3367,7 +3367,7 @@ static void skylake_update_primary_plane(struct intel_plane *plane,
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spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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if (IS_GEMINILAKE(dev_priv)) {
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if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
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I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
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PLANE_COLOR_PIPE_GAMMA_ENABLE |
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PLANE_COLOR_PIPE_CSC_ENABLE |
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@ -262,7 +262,7 @@ skl_update_plane(struct intel_plane *plane,
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spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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if (IS_GEMINILAKE(dev_priv)) {
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if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
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I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
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PLANE_COLOR_PIPE_GAMMA_ENABLE |
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PLANE_COLOR_PIPE_CSC_ENABLE |
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