mmc: sdhci-esdhc-imx: Remove the ENGcm07207 workaround
The SDHCI_QUIRK_NO_MULTIBLOCK quirk was used as a workaround for the ENGcm07207 erratum. However, it caused excruciatingly slow SD transfers (300 kB/s on average), and this erratum actually does not imply that multiple-block transfers are not supported, so this was overkill. The suggested workaround for this erratum is to set SYSCTL.RSTA, but the simple DAT line software reset (which resets the DMA circuit among others) triggered by sdhci_finish_data() in case of errors seems to be sufficient. Indeed, generating errors in a controlled manner on i.MX25 using the FEVT register right in the middle of read data transfers without this quirk shows that nothing is written to the buffer by the eSDHC past CMD12, and no extra Auto CMD12 is sent with AC12EN set, so the data transfers on AHB are properly aborted. For write data transfers, neither extra data nor extra Auto CMD12 is sent, as expected. Moreover, after intensive stress tests on i.MX25, removing SDHCI_QUIRK_NO_MULTIBLOCK seems to be safe. SDHCI_QUIRK_BROKEN_ADMA has nothing to do with ENGcm07207, so set ESDHC_FLAG_ERR004536 for the devices that had ESDHC_FLAG_ENGCM07207 set in order to continue getting SDHCI_QUIRK_BROKEN_ADMA. Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -114,11 +114,6 @@
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* exception. Bit1 of Vendor Spec register is used to fix it.
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*/
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#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
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/*
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* The flag enables the workaround for ESDHC erratum ENGcm07207 which
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* affects i.MX25 and i.MX35.
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*/
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#define ESDHC_FLAG_ENGCM07207 BIT(2)
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/*
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* The flag tells that the ESDHC controller is an USDHC block that is
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* integrated on the i.MX6 series.
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@ -134,6 +129,8 @@
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* The IP has erratum ERR004536
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* uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
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* when reading data from the card
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* This flag is also set for i.MX25 and i.MX35 in order to get
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* SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
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*/
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#define ESDHC_FLAG_ERR004536 BIT(7)
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/* The IP supports HS200 mode */
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@ -149,11 +146,11 @@ struct esdhc_soc_data {
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};
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static struct esdhc_soc_data esdhc_imx25_data = {
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.flags = ESDHC_FLAG_ENGCM07207,
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.flags = ESDHC_FLAG_ERR004536,
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};
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static struct esdhc_soc_data esdhc_imx35_data = {
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.flags = ESDHC_FLAG_ENGCM07207,
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.flags = ESDHC_FLAG_ERR004536,
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};
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static struct esdhc_soc_data esdhc_imx51_data = {
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@ -1285,11 +1282,6 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
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if (IS_ERR(imx_data->pins_default))
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dev_warn(mmc_dev(host->mmc), "could not get default state\n");
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if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
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/* Fix erratum ENGcm07207 present on i.MX25 and i.MX35 */
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host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
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| SDHCI_QUIRK_BROKEN_ADMA;
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if (esdhc_is_usdhc(imx_data)) {
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host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
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host->mmc->caps |= MMC_CAP_1_8V_DDR;
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