pata_hpt3x3: major reworking and testing
The HPT343/345 (aka 363) is a bit of a warped device. For many setups you need to access the other registers via BAR4 offsets. PIO is now rock solid, DMA isn't. Unfortunately the drivers/ide hpt34x driver is completely broken so doesn't help further debug. Signed-off-by: Alan Cox <alan@redhat.com> Cc: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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75683fe715
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66e7da4e34
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@ -309,7 +309,7 @@ config PATA_HPT3X2N
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If unsure, say N.
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If unsure, say N.
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config PATA_HPT3X3
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config PATA_HPT3X3
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tristate "HPT 343/363 PATA support (Experimental)"
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tristate "HPT 343/363 PATA support"
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depends on PCI
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depends on PCI
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help
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help
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This option enables support for the HPT 343/363
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This option enables support for the HPT 343/363
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@ -317,6 +317,14 @@ config PATA_HPT3X3
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If unsure, say N.
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If unsure, say N.
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config PATA_HPT3X3_DMA
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bool "HPT 343/363 DMA support (Experimental)"
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depends on PATA_HPT3X3
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help
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This option enables DMA support for the HPT343/363
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controllers. Enable with care as there are still some
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problems with DMA on this chipset.
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config PATA_ISAPNP
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config PATA_ISAPNP
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tristate "ISA Plug and Play PATA support (Experimental)"
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tristate "ISA Plug and Play PATA support (Experimental)"
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depends on EXPERIMENTAL && ISAPNP
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depends on EXPERIMENTAL && ISAPNP
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@ -23,7 +23,7 @@
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#include <linux/libata.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_hpt3x3"
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#define DRV_NAME "pata_hpt3x3"
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#define DRV_VERSION "0.4.3"
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#define DRV_VERSION "0.5.3"
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/**
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/**
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* hpt3x3_set_piomode - PIO setup
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* hpt3x3_set_piomode - PIO setup
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@ -59,6 +59,9 @@ static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
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*
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*
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* Set up the channel for MWDMA or UDMA modes. Much the same as with
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* Set up the channel for MWDMA or UDMA modes. Much the same as with
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* PIO, load the mode number and then set MWDMA or UDMA flag.
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* PIO, load the mode number and then set MWDMA or UDMA flag.
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*
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* 0x44 : bit 0-2 master mode, 3-5 slave mode, etc
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* 0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
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*/
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*/
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static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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@ -76,14 +79,26 @@ static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
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r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
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if (adev->dma_mode >= XFER_UDMA_0)
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if (adev->dma_mode >= XFER_UDMA_0)
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r2 |= 0x01 << dn; /* Ultra mode */
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r2 |= (0x10 << dn); /* Ultra mode */
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else
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else
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r2 |= 0x10 << dn; /* MWDMA */
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r2 |= (0x01 << dn); /* MWDMA */
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pci_write_config_dword(pdev, 0x44, r1);
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pci_write_config_dword(pdev, 0x44, r1);
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pci_write_config_dword(pdev, 0x48, r2);
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pci_write_config_dword(pdev, 0x48, r2);
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}
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}
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/**
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* hpt3x3_atapi_dma - ATAPI DMA check
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* @qc: Queued command
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*
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* Just say no - we don't do ATAPI DMA
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*/
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static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
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{
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return 1;
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}
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static struct scsi_host_template hpt3x3_sht = {
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static struct scsi_host_template hpt3x3_sht = {
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.module = THIS_MODULE,
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.name = DRV_NAME,
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@ -105,7 +120,6 @@ static struct scsi_host_template hpt3x3_sht = {
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static struct ata_port_operations hpt3x3_port_ops = {
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static struct ata_port_operations hpt3x3_port_ops = {
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.port_disable = ata_port_disable,
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.port_disable = ata_port_disable,
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.set_piomode = hpt3x3_set_piomode,
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.set_piomode = hpt3x3_set_piomode,
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.set_dmamode = hpt3x3_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_load = ata_tf_load,
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@ -124,6 +138,7 @@ static struct ata_port_operations hpt3x3_port_ops = {
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.bmdma_start = ata_bmdma_start,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.bmdma_status = ata_bmdma_status,
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.check_atapi_dma= hpt3x3_atapi_dma,
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.qc_prep = ata_qc_prep,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.qc_issue = ata_qc_issue_prot,
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@ -158,32 +173,79 @@ static void hpt3x3_init_chipset(struct pci_dev *dev)
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
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}
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}
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/**
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/**
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* hpt3x3_init_one - Initialise an HPT343/363
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* hpt3x3_init_one - Initialise an HPT343/363
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* @dev: PCI device
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* @pdev: PCI device
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* @id: Entry in match table
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* @id: Entry in match table
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*
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*
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* Perform basic initialisation. The chip has a quirk that it won't
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* Perform basic initialisation. We set the device up so we access all
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* function unless it is at XX00. The old ATA driver touched this up
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* ports via BAR4. This is neccessary to work around errata.
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* but we leave it for pci quirks to do properly.
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*/
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*/
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static int hpt3x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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{
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static int printed_version;
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static const struct ata_port_info info = {
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static const struct ata_port_info info = {
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.sht = &hpt3x3_sht,
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.sht = &hpt3x3_sht,
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.flags = ATA_FLAG_SLAVE_POSS,
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = 0x1f,
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.pio_mask = 0x1f,
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#if defined(CONFIG_PATA_HPT3X3_DMA)
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/* Further debug needed */
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.mwdma_mask = 0x07,
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.mwdma_mask = 0x07,
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.udma_mask = 0x07,
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.udma_mask = 0x07,
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#endif
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.port_ops = &hpt3x3_port_ops
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.port_ops = &hpt3x3_port_ops
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};
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};
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/* Register offsets of taskfiles in BAR4 area */
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static const u8 offset_cmd[2] = { 0x20, 0x28 };
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static const u8 offset_ctl[2] = { 0x36, 0x3E };
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const struct ata_port_info *ppi[] = { &info, NULL };
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const struct ata_port_info *ppi[] = { &info, NULL };
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struct ata_host *host;
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int i, rc;
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void __iomem *base;
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hpt3x3_init_chipset(dev);
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hpt3x3_init_chipset(pdev);
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/* Now kick off ATA set up */
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return ata_pci_init_one(dev, ppi);
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
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if (!host)
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return -ENOMEM;
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/* acquire resources and fill host */
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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/* Everything is relative to BAR4 if we set up this way */
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rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
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if (rc == -EBUSY)
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pcim_pin_device(pdev);
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if (rc)
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return rc;
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host->iomap = pcim_iomap_table(pdev);
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rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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return rc;
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rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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return rc;
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base = host->iomap[4]; /* Bus mastering base */
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for (i = 0; i < host->n_ports; i++) {
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struct ata_ioports *ioaddr = &host->ports[i]->ioaddr;
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ioaddr->cmd_addr = base + offset_cmd[i];
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ioaddr->altstatus_addr =
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ioaddr->ctl_addr = base + offset_ctl[i];
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ioaddr->scr_addr = NULL;
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ata_std_ports(ioaddr);
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ioaddr->bmdma_addr = base + 8 * i;
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}
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pci_set_master(pdev);
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return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
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&hpt3x3_sht);
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}
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}
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#ifdef CONFIG_PM
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#ifdef CONFIG_PM
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