ARM: EXYNOS: Add support AFTR mode on EXYNOS4210
This patch adds support AFTR(ARM OFF TOP RUNNING) mode in cpuidle driver. L2 cache keeps their data in this mode. This patch ports the code to the latest interfaces to save/restore CPU state inclusive of CPU PM notifiers, l2 resume and cpu_suspend/resume. Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@linaro.org> [kgene.kim@samsung.com: fixed for non-smp as per Tushar's pointing out] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Amit Daniel Kachhap
Kukjin Kim
parent
0cdf3affd3
commit
67173ca492
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@ -11,25 +11,53 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/cpuidle.h>
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#include <linux/cpu_pm.h>
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#include <linux/io.h>
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#include <linux/export.h>
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#include <linux/time.h>
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#include <asm/proc-fns.h>
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#include <asm/smp_scu.h>
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#include <asm/suspend.h>
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#include <asm/unified.h>
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#include <mach/regs-pmu.h>
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#include <mach/pmu.h>
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#include <plat/cpu.h>
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#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
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S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
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(S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
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#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
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S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
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(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
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#define S5P_CHECK_AFTR 0xFCBA0D10
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static int exynos4_enter_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index);
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static int exynos4_enter_lowpower(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index);
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static struct cpuidle_state exynos4_cpuidle_set[] = {
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static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
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[0] = {
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.enter = exynos4_enter_idle,
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.exit_latency = 1,
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.target_residency = 100000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "IDLE",
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.name = "C0",
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.desc = "ARM clock gating(WFI)",
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},
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[1] = {
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.enter = exynos4_enter_lowpower,
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.exit_latency = 300,
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.target_residency = 100000,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.name = "C1",
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.desc = "ARM power down",
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},
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};
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static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
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@ -39,9 +67,102 @@ static struct cpuidle_driver exynos4_idle_driver = {
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.owner = THIS_MODULE,
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};
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/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
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static void exynos4_set_wakeupmask(void)
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{
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__raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
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}
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static unsigned int g_pwr_ctrl, g_diag_reg;
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static void save_cpu_arch_register(void)
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{
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/*read power control register*/
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asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
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/*read diagnostic register*/
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asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
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return;
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}
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static void restore_cpu_arch_register(void)
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{
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/*write power control register*/
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asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
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/*write diagnostic register*/
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asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
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return;
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}
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static int idle_finisher(unsigned long flags)
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{
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cpu_do_idle();
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return 1;
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}
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static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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struct timeval before, after;
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int idle_time;
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unsigned long tmp;
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local_irq_disable();
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do_gettimeofday(&before);
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exynos4_set_wakeupmask();
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/* Set value of power down register for aftr mode */
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exynos4_sys_powerdown_conf(SYS_AFTR);
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__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
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__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
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save_cpu_arch_register();
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/* Setting Central Sequence Register for power down mode */
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tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
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tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
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__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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cpu_pm_enter();
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cpu_suspend(0, idle_finisher);
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#ifdef CONFIG_SMP
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scu_enable(S5P_VA_SCU);
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#endif
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cpu_pm_exit();
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restore_cpu_arch_register();
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/*
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* If PMU failed while entering sleep mode, WFI will be
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* ignored by PMU and then exiting cpu_do_idle().
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* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
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* in this situation.
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*/
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tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
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if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
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tmp |= S5P_CENTRAL_LOWPWR_CFG;
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__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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}
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/* Clear wakeup state register */
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__raw_writel(0x0, S5P_WAKEUP_STAT);
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do_gettimeofday(&after);
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local_irq_enable();
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idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
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(after.tv_usec - before.tv_usec);
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dev->last_residency = idle_time;
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return index;
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}
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static int exynos4_enter_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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int index)
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{
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struct timeval before, after;
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int idle_time;
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@ -60,6 +181,22 @@ static int exynos4_enter_idle(struct cpuidle_device *dev,
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return index;
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}
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static int exynos4_enter_lowpower(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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int new_index = index;
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/* This mode only can be entered when other core's are offline */
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if (num_online_cpus() > 1)
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new_index = drv->safe_state_index;
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if (new_index == 0)
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return exynos4_enter_idle(dev, drv, new_index);
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else
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return exynos4_enter_core0_aftr(dev, drv, new_index);
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}
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static int __init exynos4_init_cpuidle(void)
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{
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int i, max_cpuidle_state, cpu_id;
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@ -74,19 +211,25 @@ static int __init exynos4_init_cpuidle(void)
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memcpy(&drv->states[i], &exynos4_cpuidle_set[i],
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sizeof(struct cpuidle_state));
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}
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drv->safe_state_index = 0;
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cpuidle_register_driver(&exynos4_idle_driver);
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for_each_cpu(cpu_id, cpu_online_mask) {
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device = &per_cpu(exynos4_cpuidle_device, cpu_id);
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device->cpu = cpu_id;
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device->state_count = drv->state_count;
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if (cpu_id == 0)
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device->state_count = (sizeof(exynos4_cpuidle_set) /
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sizeof(struct cpuidle_state));
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else
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device->state_count = 1; /* Support IDLE only */
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if (cpuidle_register_device(device)) {
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printk(KERN_ERR "CPUidle register device failed\n,");
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return -EIO;
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}
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}
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return 0;
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}
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device_initcall(exynos4_init_cpuidle);
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@ -22,11 +22,13 @@ enum sys_powerdown {
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NUM_SYS_POWERDOWN,
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};
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extern unsigned long l2x0_regs_phys;
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struct exynos4_pmu_conf {
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void __iomem *reg;
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unsigned int val[NUM_SYS_POWERDOWN];
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};
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extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
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extern void s3c_cpu_resume(void);
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#endif /* __ASM_ARCH_PMU_H */
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