MIPS fixes for 4.17-rc7
Some MIPS fixes for 4.17: - Fix build with DEBUG_ZBOOT and MACH_JZ4770 (4.16) - Include xilfpga FDT in fitImage and stop generating dtb.o (4.15) - Fix software IO coherence on CM SMP systems (4.8) - ptrace: Fix PEEKUSR/POKEUSR to o32 FGRs (3.14) - ptrace: Expose FIR register through FP regset (3.13) - Fix typo in KVM debugfs file name (3.10) -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQS7lRNBWUYtqfDOVL41zuSGKxAj8gUCWwK2jAAKCRA1zuSGKxAj 8kXbAQD/Poo0YeGR+yWZKrJauEAkvW1Z2YwM7sb0xEQJiOLr+QEAo4nAl0HCIZoB Xzk0sWgRvr1aBAILjJkbZyGUFHHbHwc= =h7B4 -----END PGP SIGNATURE----- Merge tag 'mips_fixes_4.17_2' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips Pull MIPS fixes from James Hogan: - fix build with DEBUG_ZBOOT and MACH_JZ4770 (4.16) - include xilfpga FDT in fitImage and stop generating dtb.o (4.15) - fix software IO coherence on CM SMP systems (4.8) - ptrace: Fix PEEKUSR/POKEUSR to o32 FGRs (3.14) - ptrace: Expose FIR register through FP regset (3.13) - fix typo in KVM debugfs file name (3.10) * tag 'mips_fixes_4.17_2' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: MIPS: Fix ptrace(2) PTRACE_PEEKUSR and PTRACE_POKEUSR accesses to o32 FGRs MIPS: xilfpga: Actually include FDT in fitImage MIPS: xilfpga: Stop generating useless dtb.o KVM: Fix spelling mistake: "cop_unsuable" -> "cop_unusable" MIPS: ptrace: Expose FIR register through FP regset MIPS: Fix build with DEBUG_ZBOOT and MACH_JZ4770 MIPS: c-r4k: Fix data corruption related to cache coherence
This commit is contained in:
commit
6741c4bb38
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@ -18,9 +18,9 @@
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#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
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#endif
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#if defined(CONFIG_MACH_JZ4740) || defined(CONFIG_MACH_JZ4780)
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#include <asm/mach-jz4740/base.h>
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#define PORT(offset) (CKSEG1ADDR(JZ4740_UART0_BASE_ADDR) + (4 * offset))
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#ifdef CONFIG_MACH_INGENIC
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#define INGENIC_UART0_BASE_ADDR 0x10030000
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#define PORT(offset) (CKSEG1ADDR(INGENIC_UART0_BASE_ADDR) + (4 * offset))
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#endif
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#ifdef CONFIG_CPU_XLR
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@ -1,4 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += nexys4ddr.dtb
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obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
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@ -16,3 +16,4 @@ all-$(CONFIG_MIPS_GENERIC) := vmlinux.gz.itb
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its-y := vmlinux.its.S
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its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S
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its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S
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its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S
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@ -463,7 +463,7 @@ static int fpr_get_msa(struct task_struct *target,
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/*
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* Copy the floating-point context to the supplied NT_PRFPREG buffer.
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* Choose the appropriate helper for general registers, and then copy
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* the FCSR register separately.
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* the FCSR and FIR registers separately.
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*/
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static int fpr_get(struct task_struct *target,
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const struct user_regset *regset,
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@ -471,6 +471,7 @@ static int fpr_get(struct task_struct *target,
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void *kbuf, void __user *ubuf)
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{
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const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);
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const int fir_pos = fcr31_pos + sizeof(u32);
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int err;
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if (sizeof(target->thread.fpu.fpr[0]) == sizeof(elf_fpreg_t))
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@ -483,6 +484,12 @@ static int fpr_get(struct task_struct *target,
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err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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&target->thread.fpu.fcr31,
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fcr31_pos, fcr31_pos + sizeof(u32));
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if (err)
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return err;
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err = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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&boot_cpu_data.fpu_id,
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fir_pos, fir_pos + sizeof(u32));
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return err;
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}
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@ -531,7 +538,8 @@ static int fpr_set_msa(struct task_struct *target,
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/*
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* Copy the supplied NT_PRFPREG buffer to the floating-point context.
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* Choose the appropriate helper for general registers, and then copy
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* the FCSR register separately.
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* the FCSR register separately. Ignore the incoming FIR register
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* contents though, as the register is read-only.
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*
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* We optimize for the case where `count % sizeof(elf_fpreg_t) == 0',
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* which is supposed to have been guaranteed by the kernel before
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@ -545,6 +553,7 @@ static int fpr_set(struct task_struct *target,
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const void *kbuf, const void __user *ubuf)
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{
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const int fcr31_pos = NUM_FPU_REGS * sizeof(elf_fpreg_t);
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const int fir_pos = fcr31_pos + sizeof(u32);
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u32 fcr31;
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int err;
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@ -572,6 +581,11 @@ static int fpr_set(struct task_struct *target,
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ptrace_setfcr31(target, fcr31);
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}
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if (count > 0)
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err = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
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fir_pos,
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fir_pos + sizeof(u32));
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return err;
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}
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@ -793,7 +807,7 @@ long arch_ptrace(struct task_struct *child, long request,
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fregs = get_fpu_regs(child);
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#ifdef CONFIG_32BIT
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if (test_thread_flag(TIF_32BIT_FPREGS)) {
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if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
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/*
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* The odd registers are actually the high
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* order bits of the values stored in the even
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@ -888,7 +902,7 @@ long arch_ptrace(struct task_struct *child, long request,
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init_fp_ctx(child);
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#ifdef CONFIG_32BIT
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if (test_thread_flag(TIF_32BIT_FPREGS)) {
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if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
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/*
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* The odd registers are actually the high
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* order bits of the values stored in the even
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@ -99,7 +99,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
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break;
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}
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fregs = get_fpu_regs(child);
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if (test_thread_flag(TIF_32BIT_FPREGS)) {
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if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
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/*
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* The odd registers are actually the high
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* order bits of the values stored in the even
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@ -212,7 +212,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
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sizeof(child->thread.fpu));
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child->thread.fpu.fcr31 = 0;
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}
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if (test_thread_flag(TIF_32BIT_FPREGS)) {
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if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
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/*
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* The odd registers are actually the high
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* order bits of the values stored in the even
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@ -45,7 +45,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
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{ "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
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{ "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
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{ "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
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{ "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
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{ "cop_unusable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
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{ "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
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{ "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
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{ "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
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@ -851,9 +851,12 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
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/*
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* Either no secondary cache or the available caches don't have the
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* subset property so we have to flush the primary caches
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* explicitly
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* explicitly.
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* If we would need IPI to perform an INDEX-type operation, then
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* we have to use the HIT-type alternative as IPI cannot be used
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* here due to interrupts possibly being disabled.
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*/
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if (size >= dcache_size) {
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if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
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r4k_blast_dcache();
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} else {
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R4600_HIT_CACHEOP_WAR_IMPL;
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return;
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}
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if (size >= dcache_size) {
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if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
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r4k_blast_dcache();
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} else {
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R4600_HIT_CACHEOP_WAR_IMPL;
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