intel-iommu: Print out iommu seq_id
more info on system with more than one IOMMU Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -806,7 +806,8 @@ int alloc_iommu(struct dmar_drhd_unit *drhd)
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}
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ver = readl(iommu->reg + DMAR_VER_REG);
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pr_info("IOMMU %llx: ver %d:%d cap %llx ecap %llx\n",
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pr_info("IOMMU %d: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
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iommu->seq_id,
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(unsigned long long)drhd->reg_base_addr,
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DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
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(unsigned long long)iommu->cap,
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@ -1150,7 +1150,8 @@ static int iommu_init_domains(struct intel_iommu *iommu)
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unsigned long nlongs;
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ndomains = cap_ndoms(iommu->cap);
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pr_debug("Number of Domains supportd <%ld>\n", ndomains);
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pr_debug("IOMMU %d: Number of Domains supportd <%ld>\n", iommu->seq_id,
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ndomains);
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nlongs = BITS_TO_LONGS(ndomains);
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spin_lock_init(&iommu->lock);
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@ -2319,14 +2320,16 @@ int __init init_dmars(void)
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*/
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iommu->flush.flush_context = __iommu_flush_context;
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iommu->flush.flush_iotlb = __iommu_flush_iotlb;
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printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
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printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
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"invalidation\n",
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iommu->seq_id,
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(unsigned long long)drhd->reg_base_addr);
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} else {
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iommu->flush.flush_context = qi_flush_context;
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iommu->flush.flush_iotlb = qi_flush_iotlb;
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printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
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printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
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"invalidation\n",
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iommu->seq_id,
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(unsigned long long)drhd->reg_base_addr);
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}
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}
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@ -831,9 +831,9 @@ static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
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return -1;
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}
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printk(KERN_INFO "IOAPIC id %d under DRHD base"
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" 0x%Lx\n", scope->enumeration_id,
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drhd->address);
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printk(KERN_INFO "IOAPIC id %d under DRHD base "
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" 0x%Lx IOMMU %d\n", scope->enumeration_id,
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drhd->address, iommu->seq_id);
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ir_parse_one_ioapic_scope(scope, iommu);
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} else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) {
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