Second Round of Renesas ARM based SoC updates for v3.13
* SMP support for r8a7791 SoC * r8a7779_init_irq_extpin() for DT for r8a7779 and r8a7778 SoCs * Add HPB-DMAC to r8a7779 and r8a7778 SoCs * Add r7s72100 SoC * Make use of ARCH timer workaround on r8a7791 SoC * Add IRQC platform device support to r8a7791 SoC * Add I2C clocks and aliases for the DT mode for r8a7790 SoC * Add MAC platform device to r8a73a4 SoC -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJSVNx0AAoJENfPZGlqN0++8AgP/2lhZpPt2bClp73YdhOajNhA Vd9N8b48L7J8ERVc8aoXaVJa3y4l3gt6eVpwjamic0lTzN3tiHex+GFmLwJb44fT xZu3V2+D5YPwQ7mGbTNrRWDeg4dRE4z6CHw6mHmSr2Iq/dVPKxlb9JCfuQlKcgVx iKA1yYhB30F165izsaG6jW3bxO+afG2nr07byE43Gy+j7VBaV+LUeKS2Nr7UQ8Is 3iNf1YIXGZTXsKlonKjXVwsdBFTOUcDqwwDPmdzzO0aLMSc8Fw+GaiznK8nYXff5 zSeeoXFCdBbhloiPbe9TX+qFWk15Oswctgt82GMO4kVp+WLWFc5uRYgtUvN96TTh GL0WCIT74wNYc4voCdmuqU9FGNPHFUjb5MktN0x9AbFjz1ydE01eLDSrH7lwNHSW XJSTzdk5rLWyKAHH8pP5dMfjebRr4sAOIfNuyfzf3Y+U1BzRe9WdmoGbrFE6rV3T r2qC2jaxfKbHItbndKYeX8uhHboOD9Uid2xlFvAvGAK4qZKbuWREX/tSHSCE2RPg 9xZ4y6/M/qFxC/geAHOf/tWcoYafxrpTgOp5aBhfi70U8tSbfXPCfVsg/fR35Lbc eyoIOkSZC4mQEi7MIlPs3Jelo72+FtlUUKHYzAHhPj6pW4SwaMO5El56EA7My6DA T6Ow4Wqglujtt7J8fYs6 =4wdR -----END PGP SIGNATURE----- Merge tag 'renesas-soc2-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc From Simon Horman: Second Round of Renesas ARM based SoC updates for v3.13 * SMP support for r8a7791 SoC * r8a7779_init_irq_extpin() for DT for r8a7779 and r8a7778 SoCs * Add HPB-DMAC to r8a7779 and r8a7778 SoCs * Add r7s72100 SoC * Make use of ARCH timer workaround on r8a7791 SoC * Add IRQC platform device support to r8a7791 SoC * Add I2C clocks and aliases for the DT mode for r8a7790 SoC * Add MAC platform device to r8a73a4 SoC * tag 'renesas-soc2-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7791 SMP support ARM: shmobile: r8a7779: split r8a7779_init_irq_extpin() for DT ARM: shmobile: r8a7778: split r8a7778_init_irq_extpin() for DT ARM: shmobile: r7s72100 SCIF support ARM: shmobile: Initial r7s72100 SoC support ARM: shmobile: r8a7791 Arch timer workaround ARM: shmobile: r8a7791 IRQC platform device support ARM: shmobile: Introduce r8a7791_add_standard_devices() ARM: shmobile: Break out R-Car Gen2 setup code ARM: shmobile: r8a73a4: add a clock alias for the DMAC in DT mode ARM: shmobile: r8a7790: add I2C clocks and aliases for the DT mode ARM: shmobile: r8a7779: add HPB-DMAC support ARM: shmobile: r8a7778: add HPB-DMAC support ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it ARM: shmobile: Remove #gpio-ranges-cells DT property gpio: rcar: Remove #gpio-range-cells DT property usage ARM: shmobile: armadillo: fixup ether pinctrl naming ARM: shmobile: Lager: add Micrel KSZ8041 PHY fixup ARM: shmobile: update SDHI DT compatibility string to the <unit>-<soc> format Signed-off-by: Kevin Hilman <khilman@linaro.org>
This commit is contained in:
Kevin Hilman
commit
695e604477
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@ -9,12 +9,15 @@ compulsory and any optional properties, common to all SD/MMC drivers, as
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described in mmc.txt, can be used. Additionally the following tmio_mmc-specific
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optional bindings can be used.
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Required properties:
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- compatible: "renesas,sdhi-shmobile" - a generic sh-mobile SDHI unit
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"renesas,sdhi-sh7372" - SDHI IP on SH7372 SoC
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"renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
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"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
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"renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
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"renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
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"renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
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"renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
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Optional properties:
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- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
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When used with Renesas SDHI hardware, the following compatibility strings
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configure various model-specific properties:
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"renesas,sh7372-sdhi": (default) compatible with SH7372
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"renesas,r8a7740-sdhi": compatible with R8A7740: certain MMC/SD commands have to
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wait for the interface to become idle.
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36
arch/arm/boot/dts/r7s72100.dtsi
Normal file
36
arch/arm/boot/dts/r7s72100.dtsi
Normal file
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@ -0,0 +1,36 @@
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/*
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* Device Tree Source for the r7s72100 SoC
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/ {
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compatible = "renesas,r7s72100";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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};
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gic: interrupt-controller@e8201000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0xe8201000 0x1000>,
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<0xe8202000 0x1000>;
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};
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};
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@ -193,7 +193,7 @@
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};
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sdhi0: sdhi@ee100000 {
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compatible = "renesas,r8a73a4-sdhi";
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compatible = "renesas,sdhi-r8a73a4";
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reg = <0 0xee100000 0 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 165 4>;
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@ -202,7 +202,7 @@
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};
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sdhi1: sdhi@ee120000 {
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compatible = "renesas,r8a73a4-sdhi";
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compatible = "renesas,sdhi-r8a73a4";
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reg = <0 0xee120000 0 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 166 4>;
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@ -211,7 +211,7 @@
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};
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sdhi2: sdhi@ee140000 {
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compatible = "renesas,r8a73a4-sdhi";
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compatible = "renesas,sdhi-r8a73a4";
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reg = <0 0xee140000 0 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 167 4>;
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@ -96,6 +96,5 @@
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pfc: pfc@fffc0000 {
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compatible = "renesas,pfc-r8a7778";
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reg = <0xfffc000 0x118>;
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#gpio-range-cells = <3>;
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};
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};
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@ -188,7 +188,6 @@
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pfc: pfc@fffc0000 {
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compatible = "renesas,pfc-r8a7779";
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reg = <0xfffc0000 0x23c>;
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#gpio-range-cells = <3>;
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};
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thermal@ffc48000 {
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@ -148,11 +148,10 @@
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pfc: pfc@e6060000 {
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compatible = "renesas,pfc-r8a7790";
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reg = <0 0xe6060000 0 0x250>;
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#gpio-range-cells = <3>;
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};
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sdhi0: sdhi@ee100000 {
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compatible = "renesas,r8a7790-sdhi";
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compatible = "renesas,sdhi-r8a7790";
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reg = <0 0xee100000 0 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 165 4>;
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@ -161,7 +160,7 @@
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};
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sdhi1: sdhi@ee120000 {
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compatible = "renesas,r8a7790-sdhi";
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compatible = "renesas,sdhi-r8a7790";
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reg = <0 0xee120000 0 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 166 4>;
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@ -170,7 +169,7 @@
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};
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sdhi2: sdhi@ee140000 {
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compatible = "renesas,r8a7790-sdhi";
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compatible = "renesas,sdhi-r8a7790";
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reg = <0 0xee140000 0 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 167 4>;
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@ -179,7 +178,7 @@
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};
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sdhi3: sdhi@ee160000 {
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compatible = "renesas,r8a7790-sdhi";
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compatible = "renesas,sdhi-r8a7790";
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reg = <0 0xee160000 0 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 168 4>;
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@ -196,7 +196,7 @@
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};
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sdhi0: sdhi@ee100000 {
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compatible = "renesas,r8a7740-sdhi";
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compatible = "renesas,sdhi-r8a7740";
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reg = <0xee100000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 83 4
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@ -208,7 +208,7 @@
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/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
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sdhi1: sdhi@ee120000 {
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compatible = "renesas,r8a7740-sdhi";
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compatible = "renesas,sdhi-r8a7740";
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reg = <0xee120000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 88 4
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@ -219,7 +219,7 @@
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};
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sdhi2: sdhi@ee140000 {
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compatible = "renesas,r8a7740-sdhi";
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compatible = "renesas,sdhi-r8a7740";
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reg = <0xee140000 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 104 4
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@ -113,6 +113,12 @@ config ARCH_EMEV2
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select ARM_GIC
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select CPU_V7
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config ARCH_R7S72100
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bool "RZ/A1H (R7S72100)"
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select ARM_GIC
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select CPU_V7
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select SH_CLK_CPG
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comment "SH-Mobile Board Type"
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config MACH_APE6EVM
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@ -15,8 +15,10 @@ obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o
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obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o
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obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o
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obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o
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obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o setup-rcar-gen2.o
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obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o setup-rcar-gen2.o
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obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
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obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
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# Clock objects
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ifndef CONFIG_COMMON_CLK
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@ -30,6 +32,7 @@ obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
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obj-$(CONFIG_ARCH_R8A7791) += clock-r8a7791.o
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obj-$(CONFIG_ARCH_EMEV2) += clock-emev2.o
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obj-$(CONFIG_ARCH_R7S72100) += clock-r7s72100.o
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endif
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# SMP objects
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@ -37,6 +40,7 @@ smp-y := platsmp.o headsmp.o
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smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o platsmp-scu.o
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smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o platsmp-scu.o
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smp-$(CONFIG_ARCH_R8A7790) += smp-r8a7790.o platsmp-apmu.o
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smp-$(CONFIG_ARCH_R8A7791) += smp-r8a7791.o platsmp-apmu.o
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smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o
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# IRQ objects
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@ -1108,9 +1108,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
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PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740",
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"fsib_mclk_in", "fsib"),
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/* GETHER */
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PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
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PIN_MAP_MUX_GROUP_DEFAULT("r8a7740-gether", "pfc-r8a7740",
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"gether_mii", "gether"),
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PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
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PIN_MAP_MUX_GROUP_DEFAULT("r8a7740-gether", "pfc-r8a7740",
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"gether_int", "gether"),
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/* HDMI */
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PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740",
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@ -40,7 +40,7 @@ static const char *lager_boards_compat_dt[] __initdata = {
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DT_MACHINE_START(LAGER_DT, "lager")
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.smp = smp_ops(r8a7790_smp_ops),
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.init_early = r8a7790_init_early,
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.init_time = rcar_gen2_timer_init,
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.init_machine = lager_add_standard_devices,
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.init_time = r8a7790_timer_init,
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.dt_compat = lager_boards_compat_dt,
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MACHINE_END
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@ -29,6 +29,7 @@
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#include <linux/pinctrl/machine.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include <linux/regulator/fixed.h>
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#include <linux/regulator/machine.h>
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#include <linux/sh_eth.h>
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@ -155,6 +156,30 @@ static void __init lager_add_standard_devices(void)
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ðer_pdata, sizeof(ether_pdata));
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}
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/*
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* Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds
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* to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
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* 14-15. We have to set them back to 01 from the default 00 value each time
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* the PHY is reset. It's also important because the PHY's LED0 signal is
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* connected to SoC's ETH_LINK signal and in the PHY's default mode it will
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* bounce on and off after each packet, which we apparently want to avoid.
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*/
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static int lager_ksz8041_fixup(struct phy_device *phydev)
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{
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u16 phyctrl1 = phy_read(phydev, 0x1e);
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phyctrl1 &= ~0xc000;
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phyctrl1 |= 0x4000;
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return phy_write(phydev, 0x1e, phyctrl1);
|
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}
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static void __init lager_init(void)
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{
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lager_add_standard_devices();
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phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup);
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}
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static const char *lager_boards_compat_dt[] __initdata = {
|
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"renesas,lager",
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NULL,
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||||
|
|
@ -163,7 +188,7 @@ static const char *lager_boards_compat_dt[] __initdata = {
|
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DT_MACHINE_START(LAGER_DT, "lager")
|
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.smp = smp_ops(r8a7790_smp_ops),
|
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.init_early = r8a7790_init_early,
|
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.init_time = r8a7790_timer_init,
|
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.init_machine = lager_add_standard_devices,
|
||||
.init_time = rcar_gen2_timer_init,
|
||||
.init_machine = lager_init,
|
||||
.dt_compat = lager_boards_compat_dt,
|
||||
MACHINE_END
|
||||
|
|
|
|||
202
arch/arm/mach-shmobile/clock-r7s72100.c
Normal file
202
arch/arm/mach-shmobile/clock-r7s72100.c
Normal file
|
|
@ -0,0 +1,202 @@
|
|||
/*
|
||||
* r7a72100 clock framework support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2012 Phil Edworthy
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/r7s72100.h>
|
||||
|
||||
/* registers */
|
||||
#define FRQCR 0xfcfe0010
|
||||
#define FRQCR2 0xfcfe0014
|
||||
#define STBCR3 0xfcfe0420
|
||||
#define STBCR4 0xfcfe0424
|
||||
|
||||
#define PLL_RATE 30
|
||||
|
||||
static struct clk_mapping cpg_mapping = {
|
||||
.phys = 0xfcfe0000,
|
||||
.len = 0x1000,
|
||||
};
|
||||
|
||||
/* Fixed 32 KHz root clock for RTC */
|
||||
static struct clk r_clk = {
|
||||
.rate = 32768,
|
||||
};
|
||||
|
||||
/*
|
||||
* Default rate for the root input clock, reset this with clk_set_rate()
|
||||
* from the platform code.
|
||||
*/
|
||||
static struct clk extal_clk = {
|
||||
.rate = 13330000,
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
static unsigned long pll_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate * PLL_RATE;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops pll_clk_ops = {
|
||||
.recalc = pll_recalc,
|
||||
};
|
||||
|
||||
static struct clk pll_clk = {
|
||||
.ops = &pll_clk_ops,
|
||||
.parent = &extal_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
|
||||
static unsigned long bus_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate * 2 / 3;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops bus_clk_ops = {
|
||||
.recalc = bus_recalc,
|
||||
};
|
||||
|
||||
static struct clk bus_clk = {
|
||||
.ops = &bus_clk_ops,
|
||||
.parent = &pll_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
|
||||
static unsigned long peripheral0_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / 12;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops peripheral0_clk_ops = {
|
||||
.recalc = peripheral0_recalc,
|
||||
};
|
||||
|
||||
static struct clk peripheral0_clk = {
|
||||
.ops = &peripheral0_clk_ops,
|
||||
.parent = &pll_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
|
||||
static unsigned long peripheral1_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / 6;
|
||||
}
|
||||
|
||||
static struct sh_clk_ops peripheral1_clk_ops = {
|
||||
.recalc = peripheral1_recalc,
|
||||
};
|
||||
|
||||
static struct clk peripheral1_clk = {
|
||||
.ops = &peripheral1_clk_ops,
|
||||
.parent = &pll_clk,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
};
|
||||
|
||||
struct clk *main_clks[] = {
|
||||
&r_clk,
|
||||
&extal_clk,
|
||||
&pll_clk,
|
||||
&bus_clk,
|
||||
&peripheral0_clk,
|
||||
&peripheral1_clk,
|
||||
};
|
||||
|
||||
static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */
|
||||
static int multipliers[] = { 1, 2, 1, 1 };
|
||||
|
||||
static struct clk_div_mult_table div4_div_mult_table = {
|
||||
.divisors = div2,
|
||||
.nr_divisors = ARRAY_SIZE(div2),
|
||||
.multipliers = multipliers,
|
||||
.nr_multipliers = ARRAY_SIZE(multipliers),
|
||||
};
|
||||
|
||||
static struct clk_div4_table div4_table = {
|
||||
.div_mult_table = &div4_div_mult_table,
|
||||
};
|
||||
|
||||
enum { DIV4_I,
|
||||
DIV4_NR };
|
||||
|
||||
#define DIV4(_reg, _bit, _mask, _flags) \
|
||||
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
|
||||
|
||||
/* The mask field specifies the div2 entries that are valid */
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
|
||||
| CLK_ENABLE_ON_INIT),
|
||||
};
|
||||
|
||||
enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
|
||||
MSTP33, MSTP_NR };
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
|
||||
[MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
|
||||
[MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
|
||||
[MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
|
||||
[MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
|
||||
[MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
|
||||
[MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
|
||||
[MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
|
||||
[MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("rclk", &r_clk),
|
||||
CLKDEV_CON_ID("extal", &extal_clk),
|
||||
CLKDEV_CON_ID("pll_clk", &pll_clk),
|
||||
CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
|
||||
|
||||
/* MSTP clocks */
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
|
||||
CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
|
||||
};
|
||||
|
||||
void __init r7s72100_clock_init(void)
|
||||
{
|
||||
int k, ret = 0;
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
|
||||
|
||||
if (!ret)
|
||||
shmobile_clk_init();
|
||||
else
|
||||
panic("failed to setup rza1 clocks\n");
|
||||
}
|
||||
|
|
@ -504,7 +504,7 @@ static struct clk div6_clks[DIV6_NR] = {
|
|||
|
||||
/* MSTP */
|
||||
enum {
|
||||
MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
|
||||
MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
|
||||
MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
|
||||
MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
|
||||
MSTP411, MSTP410, MSTP409,
|
||||
|
|
@ -519,6 +519,7 @@ static struct clk mstp_clks[MSTP_NR] = {
|
|||
[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */
|
||||
[MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */
|
||||
[MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */
|
||||
[MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC */
|
||||
[MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */
|
||||
[MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
|
||||
[MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
|
||||
|
|
@ -578,6 +579,8 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
|
||||
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
|
||||
CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]),
|
||||
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
|
||||
CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
|
||||
CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@
|
|||
#define SMSTPCR5 0xe6150144
|
||||
#define SMSTPCR7 0xe615014c
|
||||
#define SMSTPCR8 0xe6150990
|
||||
#define SMSTPCR9 0xe6150994
|
||||
|
||||
#define SDCKCR 0xE6150074
|
||||
#define SD2CKCR 0xE6150078
|
||||
|
|
@ -181,6 +182,7 @@ static struct clk div6_clks[DIV6_NR] = {
|
|||
|
||||
/* MSTP */
|
||||
enum {
|
||||
MSTP931, MSTP930, MSTP929, MSTP928,
|
||||
MSTP813,
|
||||
MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
|
||||
MSTP717, MSTP716,
|
||||
|
|
@ -192,6 +194,10 @@ enum {
|
|||
};
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */
|
||||
[MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */
|
||||
[MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */
|
||||
[MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */
|
||||
[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
|
||||
[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
|
||||
[MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
|
||||
|
|
@ -271,6 +277,10 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
|
||||
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
|
||||
CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
|
||||
CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
|
||||
CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
|
||||
CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
|
||||
CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
|
||||
CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
|
||||
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
|
||||
CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
|
||||
|
|
@ -300,7 +310,7 @@ static struct clk_lookup lookups[] = {
|
|||
|
||||
void __init r8a7790_clock_init(void)
|
||||
{
|
||||
u32 mode = r8a7790_read_mode_pins();
|
||||
u32 mode = rcar_gen2_read_mode_pins();
|
||||
int k, ret = 0;
|
||||
|
||||
switch (mode & (MD(14) | MD(13))) {
|
||||
|
|
|
|||
8
arch/arm/mach-shmobile/include/mach/r7s72100.h
Normal file
8
arch/arm/mach-shmobile/include/mach/r7s72100.h
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
#ifndef __ASM_R7S72100_H__
|
||||
#define __ASM_R7S72100_H__
|
||||
|
||||
void r7s72100_add_dt_devices(void);
|
||||
void r7s72100_clock_init(void);
|
||||
void r7s72100_init_early(void);
|
||||
|
||||
#endif /* __ASM_R7S72100_H__ */
|
||||
|
|
@ -1,6 +1,15 @@
|
|||
#ifndef __ASM_R8A73A4_H__
|
||||
#define __ASM_R8A73A4_H__
|
||||
|
||||
/* DMA slave IDs */
|
||||
enum {
|
||||
SHDMA_SLAVE_INVALID,
|
||||
SHDMA_SLAVE_MMCIF0_TX,
|
||||
SHDMA_SLAVE_MMCIF0_RX,
|
||||
SHDMA_SLAVE_MMCIF1_TX,
|
||||
SHDMA_SLAVE_MMCIF1_RX,
|
||||
};
|
||||
|
||||
void r8a73a4_add_standard_devices(void);
|
||||
void r8a73a4_add_dt_devices(void);
|
||||
void r8a73a4_clock_init(void);
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
* Copyright (C) 2013 Cogent Embedded, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -21,6 +22,13 @@
|
|||
#include <linux/sh_eth.h>
|
||||
#include <linux/platform_data/camera-rcar.h>
|
||||
|
||||
/* HPB-DMA slave IDs */
|
||||
enum {
|
||||
HPBDMA_SLAVE_DUMMY,
|
||||
HPBDMA_SLAVE_SDHI0_TX,
|
||||
HPBDMA_SLAVE_SDHI0_RX,
|
||||
};
|
||||
|
||||
extern void r8a7778_add_standard_devices(void);
|
||||
extern void r8a7778_add_standard_devices_dt(void);
|
||||
extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata);
|
||||
|
|
@ -33,6 +41,7 @@ extern void r8a7778_init_delay(void);
|
|||
extern void r8a7778_init_irq_dt(void);
|
||||
extern void r8a7778_clock_init(void);
|
||||
extern void r8a7778_init_irq_extpin(int irlm);
|
||||
extern void r8a7778_init_irq_extpin_dt(int irlm);
|
||||
extern void r8a7778_pinmux_init(void);
|
||||
|
||||
extern int r8a7778_usb_phy_power(bool enable);
|
||||
|
|
|
|||
|
|
@ -6,6 +6,13 @@
|
|||
#include <linux/sh_eth.h>
|
||||
#include <linux/platform_data/camera-rcar.h>
|
||||
|
||||
/* HPB-DMA slave IDs */
|
||||
enum {
|
||||
HPBDMA_SLAVE_DUMMY,
|
||||
HPBDMA_SLAVE_SDHI0_TX,
|
||||
HPBDMA_SLAVE_SDHI0_RX,
|
||||
};
|
||||
|
||||
struct platform_device;
|
||||
|
||||
struct r8a7779_pm_ch {
|
||||
|
|
@ -26,6 +33,7 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
|
|||
|
||||
extern void r8a7779_init_delay(void);
|
||||
extern void r8a7779_init_irq_extpin(int irlm);
|
||||
extern void r8a7779_init_irq_extpin_dt(int irlm);
|
||||
extern void r8a7779_init_irq_dt(void);
|
||||
extern void r8a7779_map_io(void);
|
||||
extern void r8a7779_earlytimer_init(void);
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
#ifndef __ASM_R8A7790_H__
|
||||
#define __ASM_R8A7790_H__
|
||||
|
||||
#include <mach/rcar-gen2.h>
|
||||
|
||||
void r8a7790_add_standard_devices(void);
|
||||
void r8a7790_add_dt_devices(void);
|
||||
void r8a7790_clock_init(void);
|
||||
void r8a7790_pinmux_init(void);
|
||||
void r8a7790_init_early(void);
|
||||
void r8a7790_timer_init(void);
|
||||
extern struct smp_operations r8a7790_smp_ops;
|
||||
|
||||
#define MD(nr) BIT(nr)
|
||||
u32 r8a7790_read_mode_pins(void);
|
||||
|
||||
#endif /* __ASM_R8A7790_H__ */
|
||||
|
|
|
|||
|
|
@ -1,8 +1,10 @@
|
|||
#ifndef __ASM_R8A7791_H__
|
||||
#define __ASM_R8A7791_H__
|
||||
|
||||
void r8a7791_add_standard_devices(void);
|
||||
void r8a7791_add_dt_devices(void);
|
||||
void r8a7791_clock_init(void);
|
||||
void r8a7791_init_early(void);
|
||||
extern struct smp_operations r8a7791_smp_ops;
|
||||
|
||||
#endif /* __ASM_R8A7791_H__ */
|
||||
|
|
|
|||
8
arch/arm/mach-shmobile/include/mach/rcar-gen2.h
Normal file
8
arch/arm/mach-shmobile/include/mach/rcar-gen2.h
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
#ifndef __ASM_RCAR_GEN2_H__
|
||||
#define __ASM_RCAR_GEN2_H__
|
||||
|
||||
void rcar_gen2_timer_init(void);
|
||||
#define MD(nr) BIT(nr)
|
||||
u32 rcar_gen2_read_mode_pins(void);
|
||||
|
||||
#endif /* __ASM_RCAR_GEN2_H__ */
|
||||
88
arch/arm/mach-shmobile/setup-r7s72100.c
Normal file
88
arch/arm/mach-shmobile/setup-r7s72100.c
Normal file
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* r7s72100 processor support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/r7s72100.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#define SCIF_DATA(index, baseaddr, irq) \
|
||||
[index] = { \
|
||||
.type = PORT_SCIF, \
|
||||
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
|
||||
.scbrr_algo_id = SCBRR_ALGO_2, \
|
||||
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \
|
||||
SCSCR_REIE, \
|
||||
.mapbase = baseaddr, \
|
||||
.irqs = { irq + 1, irq + 2, irq + 3, irq }, \
|
||||
}
|
||||
|
||||
enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 };
|
||||
|
||||
static const struct plat_sci_port scif[] __initconst = {
|
||||
SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */
|
||||
SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */
|
||||
SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */
|
||||
SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */
|
||||
SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */
|
||||
SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */
|
||||
SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */
|
||||
SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */
|
||||
};
|
||||
|
||||
static inline void r7s72100_register_scif(int idx)
|
||||
{
|
||||
platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
|
||||
sizeof(struct plat_sci_port));
|
||||
}
|
||||
|
||||
void __init r7s72100_add_dt_devices(void)
|
||||
{
|
||||
r7s72100_register_scif(SCIF0);
|
||||
r7s72100_register_scif(SCIF1);
|
||||
r7s72100_register_scif(SCIF2);
|
||||
r7s72100_register_scif(SCIF3);
|
||||
r7s72100_register_scif(SCIF4);
|
||||
r7s72100_register_scif(SCIF5);
|
||||
r7s72100_register_scif(SCIF6);
|
||||
r7s72100_register_scif(SCIF7);
|
||||
}
|
||||
|
||||
void __init r7s72100_init_early(void)
|
||||
{
|
||||
shmobile_setup_delay(400, 1, 3); /* Cortex-A9 @ 400MHz */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USE_OF
|
||||
static const char *r7s72100_boards_compat_dt[] __initdata = {
|
||||
"renesas,r7s72100",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)")
|
||||
.init_early = r7s72100_init_early,
|
||||
.dt_compat = r7s72100_boards_compat_dt,
|
||||
MACHINE_END
|
||||
#endif /* CONFIG_USE_OF */
|
||||
|
|
@ -22,8 +22,10 @@
|
|||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_data/irq-renesas-irqc.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_dma.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/dma-register.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/r8a73a4.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
|
@ -199,12 +201,101 @@ void __init r8a73a4_add_dt_devices(void)
|
|||
r8a7790_register_cmt(10);
|
||||
}
|
||||
|
||||
/* DMA */
|
||||
static const struct sh_dmae_slave_config dma_slaves[] = {
|
||||
{
|
||||
.slave_id = SHDMA_SLAVE_MMCIF0_TX,
|
||||
.addr = 0xee200034,
|
||||
.chcr = CHCR_TX(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xd1,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_MMCIF0_RX,
|
||||
.addr = 0xee200034,
|
||||
.chcr = CHCR_RX(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xd2,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_MMCIF1_TX,
|
||||
.addr = 0xee220034,
|
||||
.chcr = CHCR_TX(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xe1,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_MMCIF1_RX,
|
||||
.addr = 0xee220034,
|
||||
.chcr = CHCR_RX(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xe2,
|
||||
},
|
||||
};
|
||||
|
||||
#define DMAE_CHANNEL(a, b) \
|
||||
{ \
|
||||
.offset = (a) - 0x20, \
|
||||
.dmars = (a) - 0x20 + 0x40, \
|
||||
.chclr_bit = (b), \
|
||||
.chclr_offset = 0x80 - 0x20, \
|
||||
}
|
||||
|
||||
static const struct sh_dmae_channel dma_channels[] = {
|
||||
DMAE_CHANNEL(0x8000, 0),
|
||||
DMAE_CHANNEL(0x8080, 1),
|
||||
DMAE_CHANNEL(0x8100, 2),
|
||||
DMAE_CHANNEL(0x8180, 3),
|
||||
DMAE_CHANNEL(0x8200, 4),
|
||||
DMAE_CHANNEL(0x8280, 5),
|
||||
DMAE_CHANNEL(0x8300, 6),
|
||||
DMAE_CHANNEL(0x8380, 7),
|
||||
DMAE_CHANNEL(0x8400, 8),
|
||||
DMAE_CHANNEL(0x8480, 9),
|
||||
DMAE_CHANNEL(0x8500, 10),
|
||||
DMAE_CHANNEL(0x8580, 11),
|
||||
DMAE_CHANNEL(0x8600, 12),
|
||||
DMAE_CHANNEL(0x8680, 13),
|
||||
DMAE_CHANNEL(0x8700, 14),
|
||||
DMAE_CHANNEL(0x8780, 15),
|
||||
DMAE_CHANNEL(0x8800, 16),
|
||||
DMAE_CHANNEL(0x8880, 17),
|
||||
DMAE_CHANNEL(0x8900, 18),
|
||||
DMAE_CHANNEL(0x8980, 19),
|
||||
};
|
||||
|
||||
static const struct sh_dmae_pdata dma_pdata = {
|
||||
.slave = dma_slaves,
|
||||
.slave_num = ARRAY_SIZE(dma_slaves),
|
||||
.channel = dma_channels,
|
||||
.channel_num = ARRAY_SIZE(dma_channels),
|
||||
.ts_low_shift = TS_LOW_SHIFT,
|
||||
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
|
||||
.ts_high_shift = TS_HI_SHIFT,
|
||||
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
|
||||
.ts_shift = dma_ts_shift,
|
||||
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
|
||||
.dmaor_init = DMAOR_DME,
|
||||
.chclr_present = 1,
|
||||
.chclr_bitwise = 1,
|
||||
};
|
||||
|
||||
static struct resource dma_resources[] = {
|
||||
DEFINE_RES_MEM(0xe6700020, 0x89e0),
|
||||
DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"),
|
||||
{
|
||||
/* IRQ for channels 0-19 */
|
||||
.start = gic_spi(200),
|
||||
.end = gic_spi(219),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
#define r8a73a4_register_dmac() \
|
||||
platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0, \
|
||||
dma_resources, ARRAY_SIZE(dma_resources), \
|
||||
&dma_pdata, sizeof(dma_pdata))
|
||||
|
||||
void __init r8a73a4_add_standard_devices(void)
|
||||
{
|
||||
r8a73a4_add_dt_devices();
|
||||
r8a73a4_register_irqc(0);
|
||||
r8a73a4_register_irqc(1);
|
||||
r8a73a4_register_thermal();
|
||||
r8a73a4_register_dmac();
|
||||
}
|
||||
|
||||
void __init r8a73a4_init_early(void)
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_data/dma-rcar-hpbdma.h>
|
||||
#include <linux/platform_data/gpio-rcar.h>
|
||||
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
|
@ -356,6 +357,88 @@ void __init r8a7778_add_dt_devices(void)
|
|||
r8a7778_register_tmu(1);
|
||||
}
|
||||
|
||||
/* HPB-DMA */
|
||||
|
||||
/* Asynchronous mode register (ASYNCMDR) bits */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
|
||||
|
||||
static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
|
||||
{
|
||||
.id = HPBDMA_SLAVE_SDHI0_TX,
|
||||
.addr = 0xffe4c000 + 0x30,
|
||||
.dcr = HPB_DMAE_DCR_SPDS_16BIT |
|
||||
HPB_DMAE_DCR_DMDL |
|
||||
HPB_DMAE_DCR_DPDS_16BIT,
|
||||
.rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
|
||||
HPB_DMAE_ASYNCRSTR_ASRST22 |
|
||||
HPB_DMAE_ASYNCRSTR_ASRST23,
|
||||
.mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI,
|
||||
.mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK,
|
||||
.port = 0x0D0C,
|
||||
.flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
|
||||
.dma_ch = 21,
|
||||
}, {
|
||||
.id = HPBDMA_SLAVE_SDHI0_RX,
|
||||
.addr = 0xffe4c000 + 0x30,
|
||||
.dcr = HPB_DMAE_DCR_SMDL |
|
||||
HPB_DMAE_DCR_SPDS_16BIT |
|
||||
HPB_DMAE_DCR_DPDS_16BIT,
|
||||
.rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
|
||||
HPB_DMAE_ASYNCRSTR_ASRST22 |
|
||||
HPB_DMAE_ASYNCRSTR_ASRST23,
|
||||
.mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI,
|
||||
.mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK,
|
||||
.port = 0x0D0C,
|
||||
.flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
|
||||
.dma_ch = 22,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct hpb_dmae_channel hpb_dmae_channels[] = {
|
||||
HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
|
||||
HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
|
||||
};
|
||||
|
||||
static struct hpb_dmae_pdata dma_platform_data __initdata = {
|
||||
.slaves = hpb_dmae_slaves,
|
||||
.num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
|
||||
.channels = hpb_dmae_channels,
|
||||
.num_channels = ARRAY_SIZE(hpb_dmae_channels),
|
||||
.ts_shift = {
|
||||
[XMIT_SZ_8BIT] = 0,
|
||||
[XMIT_SZ_16BIT] = 1,
|
||||
[XMIT_SZ_32BIT] = 2,
|
||||
},
|
||||
.num_hw_channels = 39,
|
||||
};
|
||||
|
||||
static struct resource hpb_dmae_resources[] __initdata = {
|
||||
/* Channel registers */
|
||||
DEFINE_RES_MEM(0xffc08000, 0x1000),
|
||||
/* Common registers */
|
||||
DEFINE_RES_MEM(0xffc09000, 0x170),
|
||||
/* Asynchronous reset registers */
|
||||
DEFINE_RES_MEM(0xffc00300, 4),
|
||||
/* Asynchronous mode registers */
|
||||
DEFINE_RES_MEM(0xffc00400, 4),
|
||||
/* IRQ for DMA channels */
|
||||
DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ),
|
||||
};
|
||||
|
||||
static void __init r8a7778_register_hpb_dmae(void)
|
||||
{
|
||||
platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
|
||||
hpb_dmae_resources,
|
||||
ARRAY_SIZE(hpb_dmae_resources),
|
||||
&dma_platform_data,
|
||||
sizeof(dma_platform_data));
|
||||
}
|
||||
|
||||
void __init r8a7778_add_standard_devices(void)
|
||||
{
|
||||
r8a7778_add_dt_devices();
|
||||
|
|
@ -366,6 +449,8 @@ void __init r8a7778_add_standard_devices(void)
|
|||
r8a7778_register_hspi(0);
|
||||
r8a7778_register_hspi(1);
|
||||
r8a7778_register_hspi(2);
|
||||
|
||||
r8a7778_register_hpb_dmae();
|
||||
}
|
||||
|
||||
void __init r8a7778_init_late(void)
|
||||
|
|
@ -391,7 +476,7 @@ static struct resource irqpin_resources[] __initdata = {
|
|||
DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
|
||||
};
|
||||
|
||||
void __init r8a7778_init_irq_extpin(int irlm)
|
||||
void __init r8a7778_init_irq_extpin_dt(int irlm)
|
||||
{
|
||||
void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
|
||||
unsigned long tmp;
|
||||
|
|
@ -409,7 +494,11 @@ void __init r8a7778_init_irq_extpin(int irlm)
|
|||
tmp |= (1 << 21); /* LVLMODE = 1 */
|
||||
iowrite32(tmp, icr0);
|
||||
iounmap(icr0);
|
||||
}
|
||||
|
||||
void __init r8a7778_init_irq_extpin(int irlm)
|
||||
{
|
||||
r8a7778_init_irq_extpin_dt(irlm);
|
||||
if (irlm)
|
||||
platform_device_register_resndata(
|
||||
&platform_bus, "renesas_intc_irqpin", -1,
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_data/dma-rcar-hpbdma.h>
|
||||
#include <linux/platform_data/gpio-rcar.h>
|
||||
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
|
@ -97,7 +98,7 @@ static struct resource irqpin0_resources[] __initdata = {
|
|||
DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
|
||||
};
|
||||
|
||||
void __init r8a7779_init_irq_extpin(int irlm)
|
||||
void __init r8a7779_init_irq_extpin_dt(int irlm)
|
||||
{
|
||||
void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
|
||||
u32 tmp;
|
||||
|
|
@ -115,7 +116,11 @@ void __init r8a7779_init_irq_extpin(int irlm)
|
|||
tmp |= (1 << 21); /* LVLMODE = 1 */
|
||||
iowrite32(tmp, icr0);
|
||||
iounmap(icr0);
|
||||
}
|
||||
|
||||
void __init r8a7779_init_irq_extpin(int irlm)
|
||||
{
|
||||
r8a7779_init_irq_extpin_dt(irlm);
|
||||
if (irlm)
|
||||
platform_device_register_resndata(
|
||||
&platform_bus, "renesas_intc_irqpin", -1,
|
||||
|
|
@ -632,6 +637,158 @@ static struct platform_device_info *vin_info_table[] __initdata = {
|
|||
&vin3_info,
|
||||
};
|
||||
|
||||
/* HPB-DMA */
|
||||
|
||||
/* Asynchronous mode register bits */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */
|
||||
|
||||
static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
|
||||
{
|
||||
.id = HPBDMA_SLAVE_SDHI0_TX,
|
||||
.addr = 0xffe4c000 + 0x30,
|
||||
.dcr = HPB_DMAE_DCR_SPDS_16BIT |
|
||||
HPB_DMAE_DCR_DMDL |
|
||||
HPB_DMAE_DCR_DPDS_16BIT,
|
||||
.rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
|
||||
HPB_DMAE_ASYNCRSTR_ASRST22 |
|
||||
HPB_DMAE_ASYNCRSTR_ASRST23,
|
||||
.mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
|
||||
HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
|
||||
.mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
|
||||
HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
|
||||
.port = 0x0D0C,
|
||||
.flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
|
||||
.dma_ch = 21,
|
||||
}, {
|
||||
.id = HPBDMA_SLAVE_SDHI0_RX,
|
||||
.addr = 0xffe4c000 + 0x30,
|
||||
.dcr = HPB_DMAE_DCR_SMDL |
|
||||
HPB_DMAE_DCR_SPDS_16BIT |
|
||||
HPB_DMAE_DCR_DPDS_16BIT,
|
||||
.rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
|
||||
HPB_DMAE_ASYNCRSTR_ASRST22 |
|
||||
HPB_DMAE_ASYNCRSTR_ASRST23,
|
||||
.mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
|
||||
HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
|
||||
.mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
|
||||
HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
|
||||
.port = 0x0D0C,
|
||||
.flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
|
||||
.dma_ch = 22,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct hpb_dmae_channel hpb_dmae_channels[] = {
|
||||
HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
|
||||
HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
|
||||
};
|
||||
|
||||
static struct hpb_dmae_pdata dma_platform_data __initdata = {
|
||||
.slaves = hpb_dmae_slaves,
|
||||
.num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
|
||||
.channels = hpb_dmae_channels,
|
||||
.num_channels = ARRAY_SIZE(hpb_dmae_channels),
|
||||
.ts_shift = {
|
||||
[XMIT_SZ_8BIT] = 0,
|
||||
[XMIT_SZ_16BIT] = 1,
|
||||
[XMIT_SZ_32BIT] = 2,
|
||||
},
|
||||
.num_hw_channels = 44,
|
||||
};
|
||||
|
||||
static struct resource hpb_dmae_resources[] __initdata = {
|
||||
/* Channel registers */
|
||||
DEFINE_RES_MEM(0xffc08000, 0x1000),
|
||||
/* Common registers */
|
||||
DEFINE_RES_MEM(0xffc09000, 0x170),
|
||||
/* Asynchronous reset registers */
|
||||
DEFINE_RES_MEM(0xffc00300, 4),
|
||||
/* Asynchronous mode registers */
|
||||
DEFINE_RES_MEM(0xffc00400, 4),
|
||||
/* IRQ for DMA channels */
|
||||
DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
|
||||
};
|
||||
|
||||
static void __init r8a7779_register_hpb_dmae(void)
|
||||
{
|
||||
platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
|
||||
hpb_dmae_resources,
|
||||
ARRAY_SIZE(hpb_dmae_resources),
|
||||
&dma_platform_data,
|
||||
sizeof(dma_platform_data));
|
||||
}
|
||||
|
||||
static struct platform_device *r8a7779_devices_dt[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
|
|
@ -665,6 +822,7 @@ void __init r8a7779_add_standard_devices(void)
|
|||
ARRAY_SIZE(r8a7779_devices_dt));
|
||||
platform_add_devices(r8a7779_standard_devices,
|
||||
ARRAY_SIZE(r8a7779_standard_devices));
|
||||
r8a7779_register_hpb_dmae();
|
||||
}
|
||||
|
||||
void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
|
@ -203,71 +202,6 @@ void __init r8a7790_add_standard_devices(void)
|
|||
r8a7790_register_thermal();
|
||||
}
|
||||
|
||||
#define MODEMR 0xe6160060
|
||||
|
||||
u32 __init r8a7790_read_mode_pins(void)
|
||||
{
|
||||
void __iomem *modemr = ioremap_nocache(MODEMR, 4);
|
||||
u32 mode;
|
||||
|
||||
BUG_ON(!modemr);
|
||||
mode = ioread32(modemr);
|
||||
iounmap(modemr);
|
||||
|
||||
return mode;
|
||||
}
|
||||
|
||||
#define CNTCR 0
|
||||
#define CNTFID0 0x20
|
||||
|
||||
void __init r8a7790_timer_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER
|
||||
u32 mode = r8a7790_read_mode_pins();
|
||||
void __iomem *base;
|
||||
int extal_mhz = 0;
|
||||
u32 freq;
|
||||
|
||||
/* At Linux boot time the r8a7790 arch timer comes up
|
||||
* with the counter disabled. Moreover, it may also report
|
||||
* a potentially incorrect fixed 13 MHz frequency. To be
|
||||
* correct these registers need to be updated to use the
|
||||
* frequency EXTAL / 2 which can be determined by the MD pins.
|
||||
*/
|
||||
|
||||
switch (mode & (MD(14) | MD(13))) {
|
||||
case 0:
|
||||
extal_mhz = 15;
|
||||
break;
|
||||
case MD(13):
|
||||
extal_mhz = 20;
|
||||
break;
|
||||
case MD(14):
|
||||
extal_mhz = 26;
|
||||
break;
|
||||
case MD(13) | MD(14):
|
||||
extal_mhz = 30;
|
||||
break;
|
||||
}
|
||||
|
||||
/* The arch timer frequency equals EXTAL / 2 */
|
||||
freq = extal_mhz * (1000000 / 2);
|
||||
|
||||
/* Remap "armgcnt address map" space */
|
||||
base = ioremap(0xe6080000, PAGE_SIZE);
|
||||
|
||||
/* Update registers with correct frequency */
|
||||
iowrite32(freq, base + CNTFID0);
|
||||
asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
|
||||
|
||||
/* make sure arch timer is started by setting bit 0 of CNTCR */
|
||||
iowrite32(1, base + CNTCR);
|
||||
iounmap(base);
|
||||
#endif /* CONFIG_ARM_ARCH_TIMER */
|
||||
|
||||
clocksource_of_init();
|
||||
}
|
||||
|
||||
void __init r8a7790_init_early(void)
|
||||
{
|
||||
#ifndef CONFIG_ARM_ARCH_TIMER
|
||||
|
|
@ -285,7 +219,7 @@ static const char * const r8a7790_boards_compat_dt[] __initconst = {
|
|||
DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
|
||||
.smp = smp_ops(r8a7790_smp_ops),
|
||||
.init_early = r8a7790_init_early,
|
||||
.init_time = r8a7790_timer_init,
|
||||
.init_time = rcar_gen2_timer_init,
|
||||
.dt_compat = r8a7790_boards_compat_dt,
|
||||
MACHINE_END
|
||||
#endif /* CONFIG_USE_OF */
|
||||
|
|
|
|||
|
|
@ -22,11 +22,13 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_data/irq-renesas-irqc.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/r8a7791.h>
|
||||
#include <mach/rcar-gen2.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#define SCIF_COMMON(scif_type, baseaddr, irq) \
|
||||
|
|
@ -109,6 +111,31 @@ static const struct resource cmt00_resources[] __initconst = {
|
|||
&cmt##idx##_platform_data, \
|
||||
sizeof(struct sh_timer_config))
|
||||
|
||||
static struct renesas_irqc_config irqc0_data = {
|
||||
.irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
|
||||
};
|
||||
|
||||
static struct resource irqc0_resources[] = {
|
||||
DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
|
||||
DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
|
||||
DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
|
||||
DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
|
||||
DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
|
||||
DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
|
||||
DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
|
||||
DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
|
||||
DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
|
||||
DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
|
||||
DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
|
||||
};
|
||||
|
||||
#define r8a7791_register_irqc(idx) \
|
||||
platform_device_register_resndata(&platform_bus, "renesas_irqc", \
|
||||
idx, irqc##idx##_resources, \
|
||||
ARRAY_SIZE(irqc##idx##_resources), \
|
||||
&irqc##idx##_data, \
|
||||
sizeof(struct renesas_irqc_config))
|
||||
|
||||
void __init r8a7791_add_dt_devices(void)
|
||||
{
|
||||
r8a7791_register_scif(SCIFA0);
|
||||
|
|
@ -129,6 +156,12 @@ void __init r8a7791_add_dt_devices(void)
|
|||
r8a7791_register_cmt(00);
|
||||
}
|
||||
|
||||
void __init r8a7791_add_standard_devices(void)
|
||||
{
|
||||
r8a7791_add_dt_devices();
|
||||
r8a7791_register_irqc(0);
|
||||
}
|
||||
|
||||
void __init r8a7791_init_early(void)
|
||||
{
|
||||
#ifndef CONFIG_ARM_ARCH_TIMER
|
||||
|
|
@ -143,7 +176,9 @@ static const char *r8a7791_boards_compat_dt[] __initdata = {
|
|||
};
|
||||
|
||||
DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
|
||||
.smp = smp_ops(r8a7791_smp_ops),
|
||||
.init_early = r8a7791_init_early,
|
||||
.init_time = rcar_gen2_timer_init,
|
||||
.dt_compat = r8a7791_boards_compat_dt,
|
||||
MACHINE_END
|
||||
#endif /* CONFIG_USE_OF */
|
||||
|
|
|
|||
91
arch/arm/mach-shmobile/setup-rcar-gen2.c
Normal file
91
arch/arm/mach-shmobile/setup-rcar-gen2.c
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* R-Car Generation 2 support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/rcar-gen2.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#define MODEMR 0xe6160060
|
||||
|
||||
u32 __init rcar_gen2_read_mode_pins(void)
|
||||
{
|
||||
void __iomem *modemr = ioremap_nocache(MODEMR, 4);
|
||||
u32 mode;
|
||||
|
||||
BUG_ON(!modemr);
|
||||
mode = ioread32(modemr);
|
||||
iounmap(modemr);
|
||||
|
||||
return mode;
|
||||
}
|
||||
|
||||
#define CNTCR 0
|
||||
#define CNTFID0 0x20
|
||||
|
||||
void __init rcar_gen2_timer_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER
|
||||
u32 mode = rcar_gen2_read_mode_pins();
|
||||
void __iomem *base;
|
||||
int extal_mhz = 0;
|
||||
u32 freq;
|
||||
|
||||
/* At Linux boot time the r8a7790 arch timer comes up
|
||||
* with the counter disabled. Moreover, it may also report
|
||||
* a potentially incorrect fixed 13 MHz frequency. To be
|
||||
* correct these registers need to be updated to use the
|
||||
* frequency EXTAL / 2 which can be determined by the MD pins.
|
||||
*/
|
||||
|
||||
switch (mode & (MD(14) | MD(13))) {
|
||||
case 0:
|
||||
extal_mhz = 15;
|
||||
break;
|
||||
case MD(13):
|
||||
extal_mhz = 20;
|
||||
break;
|
||||
case MD(14):
|
||||
extal_mhz = 26;
|
||||
break;
|
||||
case MD(13) | MD(14):
|
||||
extal_mhz = 30;
|
||||
break;
|
||||
}
|
||||
|
||||
/* The arch timer frequency equals EXTAL / 2 */
|
||||
freq = extal_mhz * (1000000 / 2);
|
||||
|
||||
/* Remap "armgcnt address map" space */
|
||||
base = ioremap(0xe6080000, PAGE_SIZE);
|
||||
|
||||
/* Update registers with correct frequency */
|
||||
iowrite32(freq, base + CNTFID0);
|
||||
asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
|
||||
|
||||
/* make sure arch timer is started by setting bit 0 of CNTCR */
|
||||
iowrite32(1, base + CNTCR);
|
||||
iounmap(base);
|
||||
#endif /* CONFIG_ARM_ARCH_TIMER */
|
||||
|
||||
clocksource_of_init();
|
||||
}
|
||||
62
arch/arm/mach-shmobile/smp-r8a7791.c
Normal file
62
arch/arm/mach-shmobile/smp-r8a7791.c
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* SMP support for r8a7791
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/r8a7791.h>
|
||||
|
||||
#define RST 0xe6160000
|
||||
#define CA15BAR 0x0020
|
||||
#define CA15RESCNT 0x0040
|
||||
#define RAM 0xe6300000
|
||||
|
||||
static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
void __iomem *p;
|
||||
u32 bar;
|
||||
|
||||
/* let APMU code install data related to shmobile_boot_vector */
|
||||
shmobile_smp_apmu_prepare_cpus(max_cpus);
|
||||
|
||||
/* RAM for jump stub, because BAR requires 256KB aligned address */
|
||||
p = ioremap_nocache(RAM, shmobile_boot_size);
|
||||
memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
|
||||
iounmap(p);
|
||||
|
||||
/* setup reset vectors */
|
||||
p = ioremap_nocache(RST, 0x63);
|
||||
bar = (RAM >> 8) & 0xfffffc00;
|
||||
writel_relaxed(bar, p + CA15BAR);
|
||||
writel_relaxed(bar | 0x10, p + CA15BAR);
|
||||
|
||||
/* enable clocks to all CPUs */
|
||||
writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | 0xa5a50000,
|
||||
p + CA15RESCNT);
|
||||
iounmap(p);
|
||||
}
|
||||
|
||||
struct smp_operations r8a7791_smp_ops __initdata = {
|
||||
.smp_prepare_cpus = r8a7791_smp_prepare_cpus,
|
||||
.smp_boot_secondary = shmobile_smp_apmu_boot_secondary,
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
.cpu_disable = shmobile_smp_cpu_disable,
|
||||
.cpu_die = shmobile_smp_apmu_cpu_die,
|
||||
.cpu_kill = shmobile_smp_apmu_cpu_kill,
|
||||
#endif
|
||||
};
|
||||
|
|
@ -293,10 +293,9 @@ static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p)
|
|||
if (pdata) {
|
||||
p->config = *pdata;
|
||||
} else if (IS_ENABLED(CONFIG_OF) && np) {
|
||||
ret = of_parse_phandle_with_args(np, "gpio-ranges",
|
||||
"#gpio-range-cells", 0, &args);
|
||||
p->config.number_of_pins = ret == 0 && args.args_count == 3
|
||||
? args.args[2]
|
||||
ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
|
||||
&args);
|
||||
p->config.number_of_pins = ret == 0 ? args.args[2]
|
||||
: RCAR_MAX_GPIO_PER_BANK;
|
||||
p->config.gpio_base = -1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -113,14 +113,14 @@ static const struct sh_mobile_sdhi_ops sdhi_ops = {
|
|||
};
|
||||
|
||||
static const struct of_device_id sh_mobile_sdhi_of_match[] = {
|
||||
{ .compatible = "renesas,shmobile-sdhi" },
|
||||
{ .compatible = "renesas,sh7372-sdhi" },
|
||||
{ .compatible = "renesas,sh73a0-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,r8a73a4-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,r8a7740-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,r8a7778-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,r8a7779-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,r8a7790-sdhi", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,sdhi-shmobile" },
|
||||
{ .compatible = "renesas,sdhi-sh7372" },
|
||||
{ .compatible = "renesas,sdhi-sh73a0", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,sdhi-r8a73a4", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,sdhi-r8a7740", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,sdhi-r8a7778", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,sdhi-r8a7779", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{ .compatible = "renesas,sdhi-r8a7790", .data = &sh_mobile_sdhi_of_cfg[0], },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match);
|
||||
|
|
|
|||
Loading…
Reference in a new issue