perf, x86: Add new AMD family 15h msrs to perfctr reservation code
This patch allows the reservation of perfctrs with new msr addresses introduced for AMD cpu family 15h (0xc0010200/0xc0010201, etc). Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1296664860-10886-4-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -46,6 +46,8 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
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/* returns the bit offset of the performance counter register */
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_AMD:
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if (msr >= MSR_F15H_PERF_CTR)
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return (msr - MSR_F15H_PERF_CTR) >> 1;
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return msr - MSR_K7_PERFCTR0;
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case X86_VENDOR_INTEL:
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if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
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@ -70,6 +72,8 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
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/* returns the bit offset of the event selection register */
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_AMD:
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if (msr >= MSR_F15H_PERF_CTL)
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return (msr - MSR_F15H_PERF_CTL) >> 1;
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return msr - MSR_K7_EVNTSEL0;
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case X86_VENDOR_INTEL:
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if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
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