tg3: Remove unused cfgspc device members
This patch removes the pci_bist and pci_hdr_type members from the device structure and removes the code that references them. They are not really used. The patch rounds out the changes by moving the pci_cmd member to plug a structure hole that would have been created. On 32-bit systems, this movement removes a subsequent structure hole later in the structure. On 64-bit systems though, the movement merely consolidates two holes into one larger hole. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -12160,7 +12160,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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{ },
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{ },
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};
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};
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u32 misc_ctrl_reg;
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u32 misc_ctrl_reg;
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u32 cacheline_sz_reg;
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u32 pci_state_reg, grc_misc_cfg;
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u32 pci_state_reg, grc_misc_cfg;
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u32 val;
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u32 val;
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u16 pci_cmd;
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u16 pci_cmd;
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@ -12330,14 +12329,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
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pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
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tp->misc_host_ctrl);
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tp->misc_host_ctrl);
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pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
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&cacheline_sz_reg);
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tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
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tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
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tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
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tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
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tp->pdev_peer = tg3_find_peer(tp);
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tp->pdev_peer = tg3_find_peer(tp);
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@ -12447,17 +12438,15 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
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!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
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tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
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tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
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pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
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&tp->pci_cacheline_sz);
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pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
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&tp->pci_lat_timer);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
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tp->pci_lat_timer < 64) {
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tp->pci_lat_timer < 64) {
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tp->pci_lat_timer = 64;
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tp->pci_lat_timer = 64;
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pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
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cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
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tp->pci_lat_timer);
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cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
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cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
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cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
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pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
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cacheline_sz_reg);
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}
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}
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if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
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if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
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@ -2676,10 +2676,9 @@ struct tg3 {
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/* PCI block */
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/* PCI block */
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u32 pci_chip_rev_id;
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u32 pci_chip_rev_id;
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u16 pci_cmd;
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u8 pci_cacheline_sz;
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u8 pci_cacheline_sz;
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u8 pci_lat_timer;
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u8 pci_lat_timer;
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u8 pci_hdr_type;
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u8 pci_bist;
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int pm_cap;
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int pm_cap;
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int msi_cap;
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int msi_cap;
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@ -2730,7 +2729,6 @@ struct tg3 {
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u32 led_ctrl;
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u32 led_ctrl;
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u32 phy_otp;
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u32 phy_otp;
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u16 pci_cmd;
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char board_part_number[24];
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char board_part_number[24];
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#define TG3_VER_SIZE 32
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#define TG3_VER_SIZE 32
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