ARM: fixes for ARM platforms
Some fallout from the 3.3. merge window as well as a couple bug fixes for older preexisting bugs that seem valid to include at this time: * sched_clock changes broke picoxcell, fix included * BSYM bugs causing issues with thumb2-built kernels on SMP * Missing module.h include on msm. * A collection of bugfixes for samsung platforms that didn't make it into the first pull requests. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPFRlTAAoJEIwa5zzehBx3vNAP/132diTVp8P5m9+fmgkyKL1Q g6Djzdp7y4sEACCuHxTGIwhusqjwFlfTU1DnjOcQrylvN/GSBEqn1Kdjp3sC++F5 +Zot4psLpcKJk94HgbGvG+kXZ+mD2DaQUybVL/O/9ShfoUK589i4LSWWTUO4Chp8 C2Vi0s64UQW8R2gt/S7LaoaN+qbbNBDQRPj+hWJ/mO15RSH5V3XgpSOGvTq6+/QK nG/kcbVTu4su2z5mOxOZRw+Wx+woEKwpu/4viy5Kfoyj7igHAnWMGww8tkFadOam 4RBGaJwWmqPGiSkAsLoRfpUDKWBwMSAO13FRiMydhEiodL7db9Ug4kddTFT/GIQf pjEz4kscYxmYVzQ4oSjp5tG65berMBUHD3Sy7VZp/htvyF/HmbLiXfseJQF2DP0s dqoZ5W0cS3sXjzaGWzjIqZt7/GlX+ulqgy2eQnHfF/D2oFIqmtMu7YXMH3hj/m4z lrgGjGhy+XzVmRNujGvHs+p4tWZh7G5Hxprs/m3juoEopgcFbNsJGJW/nLHuDahL tOJaP5zD9mptkGBMfdWfwWngpBFJcfrF9Zq2qfHgzbzRAEGWy8hOT8qK2+fad4vN 6I52axIGBFoTZjqAfs5Pg1vc4wZd/WOHA3KjxsVEvHcHLxo/inndDG6vwJoRzQwV DjtiPTl+MRjxTQmh0+qH =+GJ1 -----END PGP SIGNATURE----- Merge tag 'arm-soc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc ARM: fixes for ARM platforms Some fallout from the 3.3. merge window as well as a couple bug fixes for older preexisting bugs that seem valid to include at this time: * sched_clock changes broke picoxcell, fix included * BSYM bugs causing issues with thumb2-built kernels on SMP * Missing module.h include on msm. * A collection of bugfixes for samsung platforms that didn't make it into the first pull requests. * tag 'arm-soc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: make BSYM macro assembly only ARM: highbank: remove incorrect BSYM usage ARM: imx: remove incorrect BSYM usage ARM: exynos: remove incorrect BSYM usage ARM: ux500: add missing ENDPROC to headsmp.S ARM: msm: Add missing ENDPROC to headsmp.S ARM: versatile: Add missing ENDPROC to headsmp.S ARM: EXYNOS: Invert VCLK polarity for framebuffer on ORIGEN ARM: S3C64XX: Fix interrupt configuration for PCA935x on Cragganmore ARM: S3C64XX: Fix the memory mapped GPIOs on Cragganmore ARM: S3C64XX: Remove hsmmc1 from Cragganmore ARM: S3C64XX: Remove unconditional power domain disables ARM: SAMSUNG: Declare struct platform_device in plat/s3c64xx-spi.h ARM: SAMSUNG: dma-ops.h needs mach/dma.h ARM: SAMSUNG: Guard against multiple inclusion of plat/dma.h ARM: picoxcell: fix sched_clock() cleanup fallout ARM: msm: vreg is a module and so needs module.h
This commit is contained in:
commit
6a488979f5
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@ -37,8 +37,8 @@
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#define THUMB(x...) x
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#ifdef __ASSEMBLY__
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#define W(instr) instr.w
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#endif
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#define BSYM(sym) sym + 1
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#endif
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#else /* !CONFIG_THUMB2_KERNEL */
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@ -49,8 +49,8 @@
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#define THUMB(x...)
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#ifdef __ASSEMBLY__
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#define W(instr) instr
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#endif
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#define BSYM(sym) sym
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#endif
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#endif /* CONFIG_THUMB2_KERNEL */
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@ -36,6 +36,8 @@ pen: ldr r7, [r6]
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(exynos4_secondary_startup)
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.align 2
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1: .long .
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.long pen_release
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@ -597,7 +597,8 @@ static struct s3c_fb_pd_win origen_fb_win0 = {
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static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
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.win[0] = &origen_fb_win0,
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.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
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.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
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.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
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VIDCON1_INV_VCLK,
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.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
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};
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@ -24,7 +24,6 @@
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#include <asm/cacheflush.h>
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#include <asm/hardware/gic.h>
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#include <asm/smp_scu.h>
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#include <asm/unified.h>
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#include <mach/hardware.h>
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#include <mach/regs-clock.h>
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@ -137,7 +136,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
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__raw_writel(virt_to_phys(exynos4_secondary_startup),
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CPU1_BOOT_REG);
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gic_raise_softirq(cpumask_of(cpu), 1);
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@ -192,6 +191,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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* until it receives a soft interrupt, and then the
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* secondary CPU branches to this address.
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*/
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__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
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__raw_writel(virt_to_phys(exynos4_secondary_startup),
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CPU1_BOOT_REG);
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}
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@ -25,7 +25,6 @@
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/unified.h>
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#include <asm/smp_scu.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/timer-sp.h>
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@ -76,7 +75,7 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
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#ifdef CONFIG_SMP
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cpu = cpu_logical_map(cpu);
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#endif
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writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu));
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writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
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__cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
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outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
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HB_JUMP_TABLE_PHYS(cpu) + 15);
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@ -15,7 +15,6 @@
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <asm/unified.h>
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#define SRC_SCR 0x000
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#define SRC_GPR1 0x020
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void imx_set_cpu_jump(int cpu, void *jump_addr)
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{
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cpu = cpu_logical_map(cpu);
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writel_relaxed(BSYM(virt_to_phys(jump_addr)),
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writel_relaxed(virt_to_phys(jump_addr),
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src_base + SRC_GPR1 + cpu * 8);
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}
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@ -34,6 +34,7 @@ pen: ldr r7, [r6]
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(msm_secondary_startup)
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.align
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1: .long .
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@ -19,6 +19,7 @@
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/debugfs.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <mach/vreg.h>
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@ -67,7 +67,7 @@ static void picoxcell_add_clocksource(struct device_node *source_timer)
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static void __iomem *sched_io_base;
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unsigned u32 notrace picoxcell_read_sched_clock(void)
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static u32 picoxcell_read_sched_clock(void)
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{
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return __raw_readl(sched_io_base);
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}
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@ -17,7 +17,6 @@
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <asm/smp_scu.h>
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#include <asm/unified.h>
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#include <mach/board-eb.h>
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#include <mach/board-pb11mp.h>
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* until it receives a soft interrupt, and then the
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* secondary CPU branches to this address.
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*/
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__raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)),
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__raw_writel(virt_to_phys(versatile_secondary_startup),
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__io_address(REALVIEW_SYS_FLAGSSET));
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}
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@ -21,5 +21,6 @@
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#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
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#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 32)
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#define BANFF_PMIC_GPIO_BASE (GPIO_BOARD_START + 64)
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#define MMGPIO_GPIO_BASE (GPIO_BOARD_START + 96)
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#endif
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@ -260,6 +260,7 @@ static struct platform_device crag6410_dm9k_device = {
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static struct resource crag6410_mmgpio_resource[] = {
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[0] = {
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.name = "dat",
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.start = S3C64XX_PA_XM0CSN4 + 1,
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.end = S3C64XX_PA_XM0CSN4 + 1,
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.flags = IORESOURCE_MEM,
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.resource = crag6410_mmgpio_resource,
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.num_resources = ARRAY_SIZE(crag6410_mmgpio_resource),
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.dev.platform_data = &(struct bgpio_pdata) {
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.base = -1,
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.base = MMGPIO_GPIO_BASE,
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},
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};
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static struct platform_device *crag6410_devices[] __initdata = {
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&s3c_device_hsmmc0,
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&s3c_device_hsmmc1,
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&s3c_device_hsmmc2,
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&s3c_device_i2c0,
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&s3c_device_i2c1,
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static struct pca953x_platform_data crag6410_pca_data = {
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.gpio_base = PCA935X_GPIO_BASE,
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.irq_base = 0,
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.irq_base = -1,
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};
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/* VDDARM is controlled by DVS1 connected to GPK(0) */
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.cd_type = S3C_SDHCI_CD_PERMANENT,
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};
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static struct s3c_sdhci_platdata crag6410_hsmmc1_pdata = {
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.max_width = 4,
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.cd_type = S3C_SDHCI_CD_GPIO,
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.ext_cd_gpio = S3C64XX_GPF(11),
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};
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static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
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{
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/* Set all the necessary GPG pins to special-function 2 */
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gpio_direction_output(S3C64XX_GPF(10), 1);
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s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
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s3c_sdhci1_set_platdata(&crag6410_hsmmc1_pdata);
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s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
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s3c_i2c0_set_platdata(&i2c0_pdata);
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@ -346,23 +346,10 @@ int __init s3c64xx_pm_init(void)
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static __init int s3c64xx_pm_initcall(void)
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{
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u32 val;
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pm_cpu_prep = s3c64xx_pm_prepare;
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pm_cpu_sleep = s3c64xx_cpu_suspend;
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pm_uart_udivslot = 1;
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/*
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* Unconditionally disable power domains that contain only
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* blocks which have no mainline driver support.
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*/
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val = __raw_readl(S3C64XX_NORMAL_CFG);
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val &= ~(S3C64XX_NORMALCFG_DOMAIN_G_ON |
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S3C64XX_NORMALCFG_DOMAIN_V_ON |
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S3C64XX_NORMALCFG_DOMAIN_I_ON |
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S3C64XX_NORMALCFG_DOMAIN_P_ON);
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__raw_writel(val, S3C64XX_NORMAL_CFG);
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#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
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gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
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gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
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@ -32,6 +32,8 @@ pen: ldr r7, [r6]
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(u8500_secondary_startup)
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.align 2
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1: .long .
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.long pen_release
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@ -13,8 +13,6 @@
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/unified.h>
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#include <mach/motherboard.h>
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#define V2M_PA_CS7 0x10000000
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* secondary CPU branches to this address.
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*/
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writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
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writel(BSYM(virt_to_phys(versatile_secondary_startup)),
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writel(virt_to_phys(versatile_secondary_startup),
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MMIO_P2V(V2M_SYS_FLAGSSET));
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}
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@ -14,6 +14,7 @@
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#define __SAMSUNG_DMA_OPS_H_ __FILE__
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#include <linux/dmaengine.h>
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#include <mach/dma.h>
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struct samsung_dma_prep_info {
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enum dma_transaction_type cap;
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@ -10,6 +10,9 @@
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* published by the Free Software Foundation.
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*/
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#ifndef __PLAT_DMA_H
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#define __PLAT_DMA_H
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#include <linux/dma-mapping.h>
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enum s3c2410_dma_buffresult {
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@ -122,5 +125,6 @@ extern int s3c2410_dma_getposition(enum dma_ch channel,
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extern int s3c2410_dma_set_opfn(enum dma_ch, s3c2410_dma_opfn_t rtn);
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extern int s3c2410_dma_set_buffdone_fn(enum dma_ch, s3c2410_dma_cbfn_t rtn);
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#include <plat/dma-ops.h>
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#endif
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@ -11,6 +11,8 @@
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#ifndef __S3C64XX_PLAT_SPI_H
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#define __S3C64XX_PLAT_SPI_H
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struct platform_device;
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/**
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* struct s3c64xx_spi_csinfo - ChipSelect description
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* @fb_delay: Slave specific feedback delay.
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|
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@ -38,3 +38,4 @@ pen: ldr r7, [r6]
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.align
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1: .long .
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.long pen_release
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ENDPROC(versatile_secondary_startup)
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