clk: xgene: Silence sparse warnings
drivers/clk/clk-xgene.c:77:43: warning: incorrect type in argument 1 (different address spaces) drivers/clk/clk-xgene.c:77:43: expected void *csr drivers/clk/clk-xgene.c:77:43: got void [noderef] <asn:2>* ... drivers/clk/clk-xgene.c: In function ‘xgene_clk_enable’: drivers/clk/clk-xgene.c:237:3: warning: format ‘%LX’ expects argument of type ‘long long unsigned int’, but argument 4 has type ‘phys_addr_t’ [-Wformat] drivers/clk/clk-xgene.c:248:3: warning: format ‘%LX’ expects argument of type ‘long long unsigned int’, but argument 4 has type ‘phys_addr_t’ [-Wformat] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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52127755fe
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@ -42,12 +42,12 @@
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static DEFINE_SPINLOCK(clk_lock);
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static inline u32 xgene_clk_read(void *csr)
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static inline u32 xgene_clk_read(void __iomem *csr)
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{
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return readl_relaxed(csr);
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}
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static inline void xgene_clk_write(u32 data, void *csr)
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static inline void xgene_clk_write(u32 data, void __iomem *csr)
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{
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return writel_relaxed(data, csr);
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}
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@ -119,7 +119,7 @@ static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
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return fvco / nout;
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}
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const struct clk_ops xgene_clk_pll_ops = {
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static const struct clk_ops xgene_clk_pll_ops = {
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.is_enabled = xgene_clk_pll_is_enabled,
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.recalc_rate = xgene_clk_pll_recalc_rate,
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};
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@ -167,7 +167,7 @@ static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_ty
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{
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const char *clk_name = np->full_name;
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struct clk *clk;
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void *reg;
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void __iomem *reg;
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reg = of_iomap(np, 0);
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if (reg == NULL) {
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@ -222,20 +222,22 @@ static int xgene_clk_enable(struct clk_hw *hw)
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struct xgene_clk *pclk = to_xgene_clk(hw);
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unsigned long flags = 0;
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u32 data;
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phys_addr_t reg;
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if (pclk->lock)
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spin_lock_irqsave(pclk->lock, flags);
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if (pclk->param.csr_reg != NULL) {
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pr_debug("%s clock enabled\n", pclk->name);
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reg = __pa(pclk->param.csr_reg);
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/* First enable the clock */
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data = xgene_clk_read(pclk->param.csr_reg +
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pclk->param.reg_clk_offset);
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data |= pclk->param.reg_clk_mask;
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xgene_clk_write(data, pclk->param.csr_reg +
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pclk->param.reg_clk_offset);
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pr_debug("%s clock PADDR base 0x%016LX clk offset 0x%08X mask 0x%08X value 0x%08X\n",
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pclk->name, __pa(pclk->param.csr_reg),
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pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n",
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pclk->name, ®,
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pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
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data);
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@ -245,8 +247,8 @@ static int xgene_clk_enable(struct clk_hw *hw)
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data &= ~pclk->param.reg_csr_mask;
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xgene_clk_write(data, pclk->param.csr_reg +
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pclk->param.reg_csr_offset);
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pr_debug("%s CSR RESET PADDR base 0x%016LX csr offset 0x%08X mask 0x%08X value 0x%08X\n",
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pclk->name, __pa(pclk->param.csr_reg),
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pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n",
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pclk->name, ®,
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pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
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data);
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}
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@ -386,7 +388,7 @@ static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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return parent_rate / divider;
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}
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const struct clk_ops xgene_clk_ops = {
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static const struct clk_ops xgene_clk_ops = {
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.enable = xgene_clk_enable,
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.disable = xgene_clk_disable,
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.is_enabled = xgene_clk_is_enabled,
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@ -456,7 +458,7 @@ static void __init xgene_devclk_init(struct device_node *np)
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parameters.csr_reg = NULL;
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parameters.divider_reg = NULL;
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for (i = 0; i < 2; i++) {
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void *map_res;
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void __iomem *map_res;
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rc = of_address_to_resource(np, i, &res);
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if (rc != 0) {
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if (i == 0) {
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