pch_uart: reference clock on CM-iTC
Default clock source for UARTs on Topcliff is external UART_CLK. On CM-iTC USB_48MHz is used instead. After VCO2PLL and DIV manipulations UARTs will receive 192 MHz. Clock manipulations on Topcliff are controlled in pch_phub.c v2: redone against the linux-next tree v3: redone against linux/kernel/git/next/linux-next.git snapshot Signed-off-by: Denis Turischev <denis@compulab.co.il> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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1a738dcf6d
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6ae705b23b
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@ -27,6 +27,7 @@
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#include <linux/mutex.h>
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#include <linux/mutex.h>
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#include <linux/if_ether.h>
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#include <linux/if_ether.h>
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#include <linux/ctype.h>
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#include <linux/ctype.h>
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#include <linux/dmi.h>
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#define PHUB_STATUS 0x00 /* Status Register offset */
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#define PHUB_STATUS 0x00 /* Status Register offset */
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#define PHUB_CONTROL 0x04 /* Control Register offset */
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#define PHUB_CONTROL 0x04 /* Control Register offset */
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@ -46,6 +47,13 @@
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#define PCH_MINOR_NOS 1
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#define PCH_MINOR_NOS 1
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#define CLKCFG_CAN_50MHZ 0x12000000
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#define CLKCFG_CAN_50MHZ 0x12000000
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#define CLKCFG_CANCLK_MASK 0xFF000000
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#define CLKCFG_CANCLK_MASK 0xFF000000
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#define CLKCFG_UART_MASK 0xFFFFFF
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/* CM-iTC */
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#define CLKCFG_UART_48MHZ (1 << 16)
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#define CLKCFG_BAUDDIV (2 << 20)
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#define CLKCFG_PLL2VCO (8 << 9)
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#define CLKCFG_UARTCLKSEL (1 << 18)
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/* Macros for ML7213 */
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/* Macros for ML7213 */
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#define PCI_VENDOR_ID_ROHM 0x10db
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#define PCI_VENDOR_ID_ROHM 0x10db
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@ -618,6 +626,14 @@ static int __devinit pch_phub_probe(struct pci_dev *pdev,
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CLKCFG_CAN_50MHZ,
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CLKCFG_CAN_50MHZ,
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CLKCFG_CANCLK_MASK);
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CLKCFG_CANCLK_MASK);
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/* quirk for CM-iTC board */
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if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC"))
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pch_phub_read_modify_write_reg(chip,
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(unsigned int)CLKCFG_REG_OFFSET,
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CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
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CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
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CLKCFG_UART_MASK);
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/* set the prefech value */
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/* set the prefech value */
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iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
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iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
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/* set the interrupt delay value */
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/* set the interrupt delay value */
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@ -21,6 +21,7 @@
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#include <linux/serial_core.h>
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#include <linux/serial_core.h>
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#include <linux/interrupt.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/dmi.h>
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#include <linux/dmaengine.h>
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#include <linux/dmaengine.h>
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#include <linux/pch_dma.h>
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#include <linux/pch_dma.h>
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@ -1404,14 +1405,18 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
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if (!rxbuf)
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if (!rxbuf)
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goto init_port_free_txbuf;
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goto init_port_free_txbuf;
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base_baud = 1843200; /* 1.8432MHz */
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/* quirk for CM-iTC board */
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if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC"))
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base_baud = 192000000; /* 192.0MHz */
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switch (port_type) {
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switch (port_type) {
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case PORT_UNKNOWN:
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case PORT_UNKNOWN:
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fifosize = 256; /* EG20T/ML7213: UART0 */
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fifosize = 256; /* EG20T/ML7213: UART0 */
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base_baud = 1843200; /* 1.8432MHz */
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break;
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break;
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case PORT_8250:
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case PORT_8250:
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fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
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fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
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base_baud = 1843200; /* 1.8432MHz */
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break;
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break;
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default:
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default:
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dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
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dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
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