[ARM] nommu: confirms the CR_V bit in nommu mode
In nommu mode, the exception vector location depends on the platforms. Some of the implementations may have some special exception control forwarding method in their ROM/flash and for some of them has its own re-mapping mechanism by the h/w. This patch introduces a special configuration CONFIG_CPU_HIGH_VECTOR which turns on the CR_V bit in nommu mode. The CR_V bit is turned off by default. This feature depends on CP15 and does not supported by ARM740. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -95,7 +95,7 @@ config ARCH_MTD_XIP
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config VECTORS_BASE
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hex
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default 0xffff0000 if MMU
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default 0xffff0000 if MMU || CPU_HIGH_VECTOR
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default DRAM_BASE if REMAP_VECTORS_TO_RAM
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default 0x00000000
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help
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@ -76,6 +76,11 @@ __after_proc_init:
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#endif
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#ifdef CONFIG_CPU_ICACHE_DISABLE
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bic r0, r0, #CR_I
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#endif
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#ifdef CONFIG_CPU_HIGH_VECTOR
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orr r0, r0, #CR_V
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#else
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bic r0, r0, #CR_V
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#endif
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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#endif /* CONFIG_CPU_CP15 */
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@ -524,6 +524,18 @@ config CPU_BIG_ENDIAN
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port must properly enable any big-endian related features
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of your chipset/board/processor.
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config CPU_HIGH_VECTOR
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depends !MMU && CPU_CP15 && !CPU_ARM740T
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bool "Select the High exception vector"
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default n
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help
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Say Y here to select high exception vector(0xFFFF0000~).
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The exception vector can be vary depending on the platform
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design in nommu mode. If your platform needs to select
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high exception vector, say Y.
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Otherwise or if you are unsure, say N, and the low exception
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vector (0x00000000~) will be used.
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config CPU_ICACHE_DISABLE
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bool "Disable I-Cache (I-bit)"
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depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
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