Merge back cpufreq material for v4.16.
Rafael J. Wysocki
commit
6b3429449e
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@ -14,3 +14,22 @@ following property before the previous one:
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Example:
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compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
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Power management
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----------------
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For power management (particularly DVFS and AVS), the North Bridge
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Power Management component is needed:
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Required properties:
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- compatible : should contain "marvell,armada-3700-nb-pm", "syscon";
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- reg : the register start and length for the North Bridge
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Power Management
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Example:
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nb_pm: syscon@14000 {
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compatible = "marvell,armada-3700-nb-pm", "syscon";
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reg = <0x14000 0x60>;
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}
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@ -0,0 +1,63 @@
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Texas Instruments OMAP compatible OPP supply description
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OMAP5, DRA7, and AM57 family of SoCs have Class0 AVS eFuse registers which
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contain data that can be used to adjust voltages programmed for some of their
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supplies for more efficient operation. This binding provides the information
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needed to read these values and use them to program the main regulator during
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an OPP transitions.
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Also, some supplies may have an associated vbb-supply which is an Adaptive Body
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Bias regulator which much be transitioned in a specific sequence with regards
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to the vdd-supply and clk when making an OPP transition. By supplying two
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regulators to the device that will undergo OPP transitions we can make use
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of the multi regulator binding that is part of the OPP core described here [1]
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to describe both regulators needed by the platform.
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[1] Documentation/devicetree/bindings/opp/opp.txt
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Required Properties for Device Node:
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- vdd-supply: phandle to regulator controlling VDD supply
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- vbb-supply: phandle to regulator controlling Body Bias supply
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(Usually Adaptive Body Bias regulator)
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Required Properties for opp-supply node:
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- compatible: Should be one of:
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"ti,omap-opp-supply" - basic OPP supply controlling VDD and VBB
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"ti,omap5-opp-supply" - OMAP5+ optimized voltages in efuse(class0)VDD
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along with VBB
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"ti,omap5-core-opp-supply" - OMAP5+ optimized voltages in efuse(class0) VDD
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but no VBB.
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- reg: Address and length of the efuse register set for the device (mandatory
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only for "ti,omap5-opp-supply")
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- ti,efuse-settings: An array of u32 tuple items providing information about
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optimized efuse configuration. Each item consists of the following:
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volt: voltage in uV - reference voltage (OPP voltage)
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efuse_offseet: efuse offset from reg where the optimized voltage is stored.
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- ti,absolute-max-voltage-uv: absolute maximum voltage for the OPP supply.
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Example:
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/* Device Node (CPU) */
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cpus {
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cpu0: cpu@0 {
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device_type = "cpu";
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...
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vdd-supply = <&vcc>;
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vbb-supply = <&abb_mpu>;
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};
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};
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/* OMAP OPP Supply with Class0 registers */
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opp_supply_mpu: opp_supply@4a003b20 {
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compatible = "ti,omap5-opp-supply";
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reg = <0x4a003b20 0x8>;
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ti,efuse-settings = <
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/* uV offset */
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1060000 0x0
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1160000 0x4
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1210000 0x8
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>;
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ti,absolute-max-voltage-uv = <1500000>;
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};
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@ -1583,6 +1583,7 @@ F: arch/arm/boot/dts/kirkwood*
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F: arch/arm/configs/mvebu_*_defconfig
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F: arch/arm/mach-mvebu/
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F: arch/arm64/boot/dts/marvell/armada*
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F: drivers/cpufreq/armada-37xx-cpufreq.c
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F: drivers/cpufreq/mvebu-cpufreq.c
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F: drivers/irqchip/irq-armada-370-xp.c
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F: drivers/irqchip/irq-mvebu-*
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@ -2,6 +2,29 @@
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# ARM CPU Frequency scaling drivers
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#
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config ACPI_CPPC_CPUFREQ
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tristate "CPUFreq driver based on the ACPI CPPC spec"
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depends on ACPI_PROCESSOR
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select ACPI_CPPC_LIB
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help
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This adds a CPUFreq driver which uses CPPC methods
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as described in the ACPIv5.1 spec. CPPC stands for
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Collaborative Processor Performance Controls. It
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is based on an abstract continuous scale of CPU
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performance values which allows the remote power
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processor to flexibly optimize for power and
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performance. CPPC relies on power management firmware
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support for its operation.
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If in doubt, say N.
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config ARM_ARMADA_37XX_CPUFREQ
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tristate "Armada 37xx CPUFreq support"
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depends on ARCH_MVEBU
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help
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This adds the CPUFreq driver support for Marvell Armada 37xx SoCs.
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The Armada 37xx PMU supports 4 frequency and VDD levels.
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# big LITTLE core layer and glue drivers
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config ARM_BIG_LITTLE_CPUFREQ
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tristate "Generic ARM big LITTLE CPUfreq driver"
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@ -12,6 +35,30 @@ config ARM_BIG_LITTLE_CPUFREQ
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help
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This enables the Generic CPUfreq driver for ARM big.LITTLE platforms.
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config ARM_DT_BL_CPUFREQ
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tristate "Generic probing via DT for ARM big LITTLE CPUfreq driver"
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depends on ARM_BIG_LITTLE_CPUFREQ && OF
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help
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This enables probing via DT for Generic CPUfreq driver for ARM
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big.LITTLE platform. This gets frequency tables from DT.
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config ARM_SCPI_CPUFREQ
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tristate "SCPI based CPUfreq driver"
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depends on ARM_BIG_LITTLE_CPUFREQ && ARM_SCPI_PROTOCOL && COMMON_CLK_SCPI
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help
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This adds the CPUfreq driver support for ARM big.LITTLE platforms
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using SCPI protocol for CPU power management.
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This driver uses SCPI Message Protocol driver to interact with the
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firmware providing the CPU DVFS functionality.
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config ARM_VEXPRESS_SPC_CPUFREQ
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tristate "Versatile Express SPC based CPUfreq driver"
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depends on ARM_BIG_LITTLE_CPUFREQ && ARCH_VEXPRESS_SPC
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help
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This add the CPUfreq driver support for Versatile Express
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big.LITTLE platforms using SPC for power management.
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config ARM_BRCMSTB_AVS_CPUFREQ
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tristate "Broadcom STB AVS CPUfreq driver"
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depends on ARCH_BRCMSTB || COMPILE_TEST
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@ -33,20 +80,6 @@ config ARM_BRCMSTB_AVS_CPUFREQ_DEBUG
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If in doubt, say N.
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config ARM_DT_BL_CPUFREQ
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tristate "Generic probing via DT for ARM big LITTLE CPUfreq driver"
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depends on ARM_BIG_LITTLE_CPUFREQ && OF
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help
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This enables probing via DT for Generic CPUfreq driver for ARM
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big.LITTLE platform. This gets frequency tables from DT.
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config ARM_VEXPRESS_SPC_CPUFREQ
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tristate "Versatile Express SPC based CPUfreq driver"
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depends on ARM_BIG_LITTLE_CPUFREQ && ARCH_VEXPRESS_SPC
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help
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This add the CPUfreq driver support for Versatile Express
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big.LITTLE platforms using SPC for power management.
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config ARM_EXYNOS5440_CPUFREQ
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tristate "SAMSUNG EXYNOS5440"
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depends on SOC_EXYNOS5440
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@ -205,16 +238,6 @@ config ARM_SA1100_CPUFREQ
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config ARM_SA1110_CPUFREQ
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bool
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config ARM_SCPI_CPUFREQ
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tristate "SCPI based CPUfreq driver"
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depends on ARM_BIG_LITTLE_CPUFREQ && ARM_SCPI_PROTOCOL && COMMON_CLK_SCPI
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help
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This adds the CPUfreq driver support for ARM big.LITTLE platforms
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using SCPI protocol for CPU power management.
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This driver uses SCPI Message Protocol driver to interact with the
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firmware providing the CPU DVFS functionality.
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config ARM_SPEAR_CPUFREQ
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bool "SPEAr CPUFreq support"
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depends on PLAT_SPEAR
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@ -275,20 +298,3 @@ config ARM_PXA2xx_CPUFREQ
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This add the CPUFreq driver support for Intel PXA2xx SOCs.
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If in doubt, say N.
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config ACPI_CPPC_CPUFREQ
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tristate "CPUFreq driver based on the ACPI CPPC spec"
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depends on ACPI_PROCESSOR
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select ACPI_CPPC_LIB
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default n
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help
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This adds a CPUFreq driver which uses CPPC methods
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as described in the ACPIv5.1 spec. CPPC stands for
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Collaborative Processor Performance Controls. It
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is based on an abstract continuous scale of CPU
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performance values which allows the remote power
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processor to flexibly optimize for power and
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performance. CPPC relies on power management firmware
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support for its operation.
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If in doubt, say N.
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@ -52,23 +52,26 @@ obj-$(CONFIG_ARM_BIG_LITTLE_CPUFREQ) += arm_big_little.o
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# LITTLE drivers, so that it is probed last.
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obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o
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obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ) += armada-37xx-cpufreq.o
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obj-$(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ) += brcmstb-avs-cpufreq.o
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obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o
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obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
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obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
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obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
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obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
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obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
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obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o
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obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
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obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
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obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
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obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
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obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += s3c24xx-cpufreq.o
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obj-$(CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS) += s3c24xx-cpufreq-debugfs.o
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obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
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obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o
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obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o
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obj-$(CONFIG_ARM_S3C2440_CPUFREQ) += s3c2440-cpufreq.o
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obj-$(CONFIG_ARM_S3C64XX_CPUFREQ) += s3c64xx-cpufreq.o
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obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += s3c24xx-cpufreq.o
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obj-$(CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS) += s3c24xx-cpufreq-debugfs.o
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obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o
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obj-$(CONFIG_ARM_SA1100_CPUFREQ) += sa1100-cpufreq.o
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obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o
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@ -81,8 +84,6 @@ obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o
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obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += tegra186-cpufreq.o
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obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-cpufreq.o
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obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o
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obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o
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obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
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##################################################################################
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@ -0,0 +1,241 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* CPU frequency scaling support for Armada 37xx platform.
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*
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* Copyright (C) 2017 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*/
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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/* Power management in North Bridge register set */
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#define ARMADA_37XX_NB_L0L1 0x18
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#define ARMADA_37XX_NB_L2L3 0x1C
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#define ARMADA_37XX_NB_TBG_DIV_OFF 13
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#define ARMADA_37XX_NB_TBG_DIV_MASK 0x7
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#define ARMADA_37XX_NB_CLK_SEL_OFF 11
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#define ARMADA_37XX_NB_CLK_SEL_MASK 0x1
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#define ARMADA_37XX_NB_CLK_SEL_TBG 0x1
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#define ARMADA_37XX_NB_TBG_SEL_OFF 9
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#define ARMADA_37XX_NB_TBG_SEL_MASK 0x3
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#define ARMADA_37XX_NB_VDD_SEL_OFF 6
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#define ARMADA_37XX_NB_VDD_SEL_MASK 0x3
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#define ARMADA_37XX_NB_CONFIG_SHIFT 16
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#define ARMADA_37XX_NB_DYN_MOD 0x24
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#define ARMADA_37XX_NB_CLK_SEL_EN BIT(26)
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#define ARMADA_37XX_NB_TBG_EN BIT(28)
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#define ARMADA_37XX_NB_DIV_EN BIT(29)
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#define ARMADA_37XX_NB_VDD_EN BIT(30)
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#define ARMADA_37XX_NB_DFS_EN BIT(31)
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#define ARMADA_37XX_NB_CPU_LOAD 0x30
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#define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3
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#define ARMADA_37XX_DVFS_LOAD_0 0
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#define ARMADA_37XX_DVFS_LOAD_1 1
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#define ARMADA_37XX_DVFS_LOAD_2 2
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#define ARMADA_37XX_DVFS_LOAD_3 3
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/*
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* On Armada 37xx the Power management manages 4 level of CPU load,
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* each level can be associated with a CPU clock source, a CPU
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* divider, a VDD level, etc...
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*/
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#define LOAD_LEVEL_NR 4
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struct armada_37xx_dvfs {
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u32 cpu_freq_max;
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u8 divider[LOAD_LEVEL_NR];
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};
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static struct armada_37xx_dvfs armada_37xx_dvfs[] = {
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{.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
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{.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
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{.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
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{.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
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};
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static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(armada_37xx_dvfs); i++) {
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if (freq == armada_37xx_dvfs[i].cpu_freq_max)
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return &armada_37xx_dvfs[i];
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}
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pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000);
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return NULL;
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}
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/*
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* Setup the four level managed by the hardware. Once the four level
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* will be configured then the DVFS will be enabled.
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*/
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static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
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struct clk *clk, u8 *divider)
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{
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int load_lvl;
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struct clk *parent;
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for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
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unsigned int reg, mask, val, offset = 0;
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if (load_lvl <= ARMADA_37XX_DVFS_LOAD_1)
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reg = ARMADA_37XX_NB_L0L1;
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else
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reg = ARMADA_37XX_NB_L2L3;
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if (load_lvl == ARMADA_37XX_DVFS_LOAD_0 ||
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load_lvl == ARMADA_37XX_DVFS_LOAD_2)
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offset += ARMADA_37XX_NB_CONFIG_SHIFT;
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/* Set cpu clock source, for all the level we use TBG */
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val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF;
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mask = (ARMADA_37XX_NB_CLK_SEL_MASK
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<< ARMADA_37XX_NB_CLK_SEL_OFF);
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/*
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* Set cpu divider based on the pre-computed array in
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* order to have balanced step.
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*/
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val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
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mask |= (ARMADA_37XX_NB_TBG_DIV_MASK
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<< ARMADA_37XX_NB_TBG_DIV_OFF);
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/* Set VDD divider which is actually the load level. */
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val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF;
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mask |= (ARMADA_37XX_NB_VDD_SEL_MASK
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<< ARMADA_37XX_NB_VDD_SEL_OFF);
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val <<= offset;
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mask <<= offset;
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regmap_update_bits(base, reg, mask, val);
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}
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/*
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* Set cpu clock source, for all the level we keep the same
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* clock source that the one already configured. For this one
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* we need to use the clock framework
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*/
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parent = clk_get_parent(clk);
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clk_set_parent(clk, parent);
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}
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static void __init armada37xx_cpufreq_disable_dvfs(struct regmap *base)
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{
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unsigned int reg = ARMADA_37XX_NB_DYN_MOD,
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mask = ARMADA_37XX_NB_DFS_EN;
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regmap_update_bits(base, reg, mask, 0);
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||||
}
|
||||
|
||||
static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base)
|
||||
{
|
||||
unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD,
|
||||
mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
|
||||
|
||||
/* Start with the highest load (0) */
|
||||
val = ARMADA_37XX_DVFS_LOAD_0;
|
||||
regmap_update_bits(base, reg, mask, val);
|
||||
|
||||
/* Now enable DVFS for the CPUs */
|
||||
reg = ARMADA_37XX_NB_DYN_MOD;
|
||||
mask = ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN |
|
||||
ARMADA_37XX_NB_DIV_EN | ARMADA_37XX_NB_VDD_EN |
|
||||
ARMADA_37XX_NB_DFS_EN;
|
||||
|
||||
regmap_update_bits(base, reg, mask, mask);
|
||||
}
|
||||
|
||||
static int __init armada37xx_cpufreq_driver_init(void)
|
||||
{
|
||||
struct armada_37xx_dvfs *dvfs;
|
||||
struct platform_device *pdev;
|
||||
unsigned int cur_frequency;
|
||||
struct regmap *nb_pm_base;
|
||||
struct device *cpu_dev;
|
||||
int load_lvl, ret;
|
||||
struct clk *clk;
|
||||
|
||||
nb_pm_base =
|
||||
syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
|
||||
|
||||
if (IS_ERR(nb_pm_base))
|
||||
return -ENODEV;
|
||||
|
||||
/* Before doing any configuration on the DVFS first, disable it */
|
||||
armada37xx_cpufreq_disable_dvfs(nb_pm_base);
|
||||
|
||||
/*
|
||||
* On CPU 0 register the operating points supported (which are
|
||||
* the nominal CPU frequency and full integer divisions of
|
||||
* it).
|
||||
*/
|
||||
cpu_dev = get_cpu_device(0);
|
||||
if (!cpu_dev) {
|
||||
dev_err(cpu_dev, "Cannot get CPU\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
clk = clk_get(cpu_dev, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(cpu_dev, "Cannot get clock for CPU0\n");
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
/* Get nominal (current) CPU frequency */
|
||||
cur_frequency = clk_get_rate(clk);
|
||||
if (!cur_frequency) {
|
||||
dev_err(cpu_dev, "Failed to get clock rate for CPU\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dvfs = armada_37xx_cpu_freq_info_get(cur_frequency);
|
||||
if (!dvfs)
|
||||
return -EINVAL;
|
||||
|
||||
armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
|
||||
|
||||
for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
|
||||
load_lvl++) {
|
||||
unsigned long freq = cur_frequency / dvfs->divider[load_lvl];
|
||||
|
||||
ret = dev_pm_opp_add(cpu_dev, freq, 0);
|
||||
if (ret) {
|
||||
/* clean-up the already added opp before leaving */
|
||||
while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
|
||||
freq = cur_frequency / dvfs->divider[load_lvl];
|
||||
dev_pm_opp_remove(cpu_dev, freq);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
/* Now that everything is setup, enable the DVFS at hardware level */
|
||||
armada37xx_cpufreq_enable_dvfs(nb_pm_base);
|
||||
|
||||
pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
|
||||
|
||||
return PTR_ERR_OR_ZERO(pdev);
|
||||
}
|
||||
/* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
|
||||
late_initcall(armada37xx_cpufreq_driver_init);
|
||||
|
||||
MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
|
||||
MODULE_DESCRIPTION("Armada 37xx cpufreq driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -108,6 +108,14 @@ static const struct of_device_id blacklist[] __initconst = {
|
|||
|
||||
{ .compatible = "marvell,armadaxp", },
|
||||
|
||||
{ .compatible = "mediatek,mt2701", },
|
||||
{ .compatible = "mediatek,mt2712", },
|
||||
{ .compatible = "mediatek,mt7622", },
|
||||
{ .compatible = "mediatek,mt7623", },
|
||||
{ .compatible = "mediatek,mt817x", },
|
||||
{ .compatible = "mediatek,mt8173", },
|
||||
{ .compatible = "mediatek,mt8176", },
|
||||
|
||||
{ .compatible = "nvidia,tegra124", },
|
||||
|
||||
{ .compatible = "st,stih407", },
|
||||
|
|
|
|||
|
|
@ -601,19 +601,18 @@ static struct cpufreq_governor *find_governor(const char *str_governor)
|
|||
/**
|
||||
* cpufreq_parse_governor - parse a governor string
|
||||
*/
|
||||
static int cpufreq_parse_governor(char *str_governor, unsigned int *policy,
|
||||
struct cpufreq_governor **governor)
|
||||
static int cpufreq_parse_governor(char *str_governor,
|
||||
struct cpufreq_policy *policy)
|
||||
{
|
||||
int err = -EINVAL;
|
||||
|
||||
if (cpufreq_driver->setpolicy) {
|
||||
if (!strncasecmp(str_governor, "performance", CPUFREQ_NAME_LEN)) {
|
||||
*policy = CPUFREQ_POLICY_PERFORMANCE;
|
||||
err = 0;
|
||||
} else if (!strncasecmp(str_governor, "powersave",
|
||||
CPUFREQ_NAME_LEN)) {
|
||||
*policy = CPUFREQ_POLICY_POWERSAVE;
|
||||
err = 0;
|
||||
policy->policy = CPUFREQ_POLICY_PERFORMANCE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!strncasecmp(str_governor, "powersave", CPUFREQ_NAME_LEN)) {
|
||||
policy->policy = CPUFREQ_POLICY_POWERSAVE;
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
struct cpufreq_governor *t;
|
||||
|
|
@ -621,26 +620,31 @@ static int cpufreq_parse_governor(char *str_governor, unsigned int *policy,
|
|||
mutex_lock(&cpufreq_governor_mutex);
|
||||
|
||||
t = find_governor(str_governor);
|
||||
|
||||
if (t == NULL) {
|
||||
if (!t) {
|
||||
int ret;
|
||||
|
||||
mutex_unlock(&cpufreq_governor_mutex);
|
||||
|
||||
ret = request_module("cpufreq_%s", str_governor);
|
||||
if (ret)
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&cpufreq_governor_mutex);
|
||||
|
||||
if (ret == 0)
|
||||
t = find_governor(str_governor);
|
||||
}
|
||||
|
||||
if (t != NULL) {
|
||||
*governor = t;
|
||||
err = 0;
|
||||
t = find_governor(str_governor);
|
||||
}
|
||||
if (t && !try_module_get(t->owner))
|
||||
t = NULL;
|
||||
|
||||
mutex_unlock(&cpufreq_governor_mutex);
|
||||
|
||||
if (t) {
|
||||
policy->governor = t;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return err;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -760,11 +764,14 @@ static ssize_t store_scaling_governor(struct cpufreq_policy *policy,
|
|||
if (ret != 1)
|
||||
return -EINVAL;
|
||||
|
||||
if (cpufreq_parse_governor(str_governor, &new_policy.policy,
|
||||
&new_policy.governor))
|
||||
if (cpufreq_parse_governor(str_governor, &new_policy))
|
||||
return -EINVAL;
|
||||
|
||||
ret = cpufreq_set_policy(policy, &new_policy);
|
||||
|
||||
if (new_policy.governor)
|
||||
module_put(new_policy.governor->owner);
|
||||
|
||||
return ret ? ret : count;
|
||||
}
|
||||
|
||||
|
|
@ -1044,8 +1051,7 @@ static int cpufreq_init_policy(struct cpufreq_policy *policy)
|
|||
if (policy->last_policy)
|
||||
new_policy.policy = policy->last_policy;
|
||||
else
|
||||
cpufreq_parse_governor(gov->name, &new_policy.policy,
|
||||
NULL);
|
||||
cpufreq_parse_governor(gov->name, &new_policy);
|
||||
}
|
||||
/* set default policy */
|
||||
return cpufreq_set_policy(policy, &new_policy);
|
||||
|
|
@ -2160,7 +2166,6 @@ void cpufreq_unregister_governor(struct cpufreq_governor *governor)
|
|||
mutex_lock(&cpufreq_governor_mutex);
|
||||
list_del(&governor->governor_list);
|
||||
mutex_unlock(&cpufreq_governor_mutex);
|
||||
return;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cpufreq_unregister_governor);
|
||||
|
||||
|
|
|
|||
|
|
@ -894,7 +894,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
|
|||
if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
|
||||
longhaul_setup_voltagescaling();
|
||||
|
||||
policy->cpuinfo.transition_latency = 200000; /* nsec */
|
||||
policy->transition_delay_us = 200000; /* usec */
|
||||
|
||||
return cpufreq_table_validate_and_show(policy, longhaul_table);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -574,6 +574,7 @@ static struct platform_driver mtk_cpufreq_platdrv = {
|
|||
/* List of machines supported by this driver */
|
||||
static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
|
||||
{ .compatible = "mediatek,mt2701", },
|
||||
{ .compatible = "mediatek,mt2712", },
|
||||
{ .compatible = "mediatek,mt7622", },
|
||||
{ .compatible = "mediatek,mt7623", },
|
||||
{ .compatible = "mediatek,mt817x", },
|
||||
|
|
|
|||
|
|
@ -76,12 +76,6 @@ static int __init armada_xp_pmsu_cpufreq_init(void)
|
|||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
/*
|
||||
* In case of a failure of dev_pm_opp_add(), we don't
|
||||
* bother with cleaning up the registered OPP (there's
|
||||
* no function to do so), and simply cancel the
|
||||
* registration of the cpufreq device.
|
||||
*/
|
||||
ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk), 0);
|
||||
if (ret) {
|
||||
clk_put(clk);
|
||||
|
|
@ -91,7 +85,8 @@ static int __init armada_xp_pmsu_cpufreq_init(void)
|
|||
ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk) / 2, 0);
|
||||
if (ret) {
|
||||
clk_put(clk);
|
||||
return ret;
|
||||
dev_err(cpu_dev, "Failed to register OPPs\n");
|
||||
goto opp_register_failed;
|
||||
}
|
||||
|
||||
ret = dev_pm_opp_set_sharing_cpus(cpu_dev,
|
||||
|
|
@ -99,9 +94,16 @@ static int __init armada_xp_pmsu_cpufreq_init(void)
|
|||
if (ret)
|
||||
dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n",
|
||||
__func__, ret);
|
||||
clk_put(clk);
|
||||
}
|
||||
|
||||
platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
|
||||
return 0;
|
||||
|
||||
opp_register_failed:
|
||||
/* As registering has failed remove all the opp for all cpus */
|
||||
dev_pm_opp_cpumask_remove_table(cpu_possible_mask);
|
||||
|
||||
return ret;
|
||||
}
|
||||
device_initcall(armada_xp_pmsu_cpufreq_init);
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/cpu.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
|
@ -50,6 +51,7 @@ struct ti_cpufreq_soc_data {
|
|||
unsigned long efuse_mask;
|
||||
unsigned long efuse_shift;
|
||||
unsigned long rev_offset;
|
||||
bool multi_regulator;
|
||||
};
|
||||
|
||||
struct ti_cpufreq_data {
|
||||
|
|
@ -57,6 +59,7 @@ struct ti_cpufreq_data {
|
|||
struct device_node *opp_node;
|
||||
struct regmap *syscon;
|
||||
const struct ti_cpufreq_soc_data *soc_data;
|
||||
struct opp_table *opp_table;
|
||||
};
|
||||
|
||||
static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data,
|
||||
|
|
@ -95,6 +98,7 @@ static struct ti_cpufreq_soc_data am3x_soc_data = {
|
|||
.efuse_offset = 0x07fc,
|
||||
.efuse_mask = 0x1fff,
|
||||
.rev_offset = 0x600,
|
||||
.multi_regulator = false,
|
||||
};
|
||||
|
||||
static struct ti_cpufreq_soc_data am4x_soc_data = {
|
||||
|
|
@ -103,6 +107,7 @@ static struct ti_cpufreq_soc_data am4x_soc_data = {
|
|||
.efuse_offset = 0x0610,
|
||||
.efuse_mask = 0x3f,
|
||||
.rev_offset = 0x600,
|
||||
.multi_regulator = false,
|
||||
};
|
||||
|
||||
static struct ti_cpufreq_soc_data dra7_soc_data = {
|
||||
|
|
@ -111,6 +116,7 @@ static struct ti_cpufreq_soc_data dra7_soc_data = {
|
|||
.efuse_mask = 0xf80000,
|
||||
.efuse_shift = 19,
|
||||
.rev_offset = 0x204,
|
||||
.multi_regulator = true,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -195,12 +201,14 @@ static const struct of_device_id ti_cpufreq_of_match[] = {
|
|||
{},
|
||||
};
|
||||
|
||||
static int ti_cpufreq_init(void)
|
||||
static int ti_cpufreq_probe(struct platform_device *pdev)
|
||||
{
|
||||
u32 version[VERSION_COUNT];
|
||||
struct device_node *np;
|
||||
const struct of_device_id *match;
|
||||
struct opp_table *ti_opp_table;
|
||||
struct ti_cpufreq_data *opp_data;
|
||||
const char * const reg_names[] = {"vdd", "vbb"};
|
||||
int ret;
|
||||
|
||||
np = of_find_node_by_path("/");
|
||||
|
|
@ -247,16 +255,29 @@ static int ti_cpufreq_init(void)
|
|||
if (ret)
|
||||
goto fail_put_node;
|
||||
|
||||
ret = PTR_ERR_OR_ZERO(dev_pm_opp_set_supported_hw(opp_data->cpu_dev,
|
||||
version, VERSION_COUNT));
|
||||
if (ret) {
|
||||
ti_opp_table = dev_pm_opp_set_supported_hw(opp_data->cpu_dev,
|
||||
version, VERSION_COUNT);
|
||||
if (IS_ERR(ti_opp_table)) {
|
||||
dev_err(opp_data->cpu_dev,
|
||||
"Failed to set supported hardware\n");
|
||||
ret = PTR_ERR(ti_opp_table);
|
||||
goto fail_put_node;
|
||||
}
|
||||
|
||||
of_node_put(opp_data->opp_node);
|
||||
opp_data->opp_table = ti_opp_table;
|
||||
|
||||
if (opp_data->soc_data->multi_regulator) {
|
||||
ti_opp_table = dev_pm_opp_set_regulators(opp_data->cpu_dev,
|
||||
reg_names,
|
||||
ARRAY_SIZE(reg_names));
|
||||
if (IS_ERR(ti_opp_table)) {
|
||||
dev_pm_opp_put_supported_hw(opp_data->opp_table);
|
||||
ret = PTR_ERR(ti_opp_table);
|
||||
goto fail_put_node;
|
||||
}
|
||||
}
|
||||
|
||||
of_node_put(opp_data->opp_node);
|
||||
register_cpufreq_dt:
|
||||
platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
|
||||
|
||||
|
|
@ -269,4 +290,22 @@ free_opp_data:
|
|||
|
||||
return ret;
|
||||
}
|
||||
device_initcall(ti_cpufreq_init);
|
||||
|
||||
static int ti_cpufreq_init(void)
|
||||
{
|
||||
platform_device_register_simple("ti-cpufreq", -1, NULL, 0);
|
||||
return 0;
|
||||
}
|
||||
module_init(ti_cpufreq_init);
|
||||
|
||||
static struct platform_driver ti_cpufreq_driver = {
|
||||
.probe = ti_cpufreq_probe,
|
||||
.driver = {
|
||||
.name = "ti-cpufreq",
|
||||
},
|
||||
};
|
||||
module_platform_driver(ti_cpufreq_driver);
|
||||
|
||||
MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver");
|
||||
MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
|
|
@ -2,3 +2,4 @@ ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG
|
|||
obj-y += core.o cpu.o
|
||||
obj-$(CONFIG_OF) += of.o
|
||||
obj-$(CONFIG_DEBUG_FS) += debugfs.o
|
||||
obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-opp-supply.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,425 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Nishanth Menon <nm@ti.com>
|
||||
* Dave Gerlach <d-gerlach@ti.com>
|
||||
*
|
||||
* TI OPP supply driver that provides override into the regulator control
|
||||
* for generic opp core to handle devices with ABB regulator and/or
|
||||
* SmartReflex Class0.
|
||||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/cpufreq.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_opp.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
/**
|
||||
* struct ti_opp_supply_optimum_voltage_table - optimized voltage table
|
||||
* @reference_uv: reference voltage (usually Nominal voltage)
|
||||
* @optimized_uv: Optimized voltage from efuse
|
||||
*/
|
||||
struct ti_opp_supply_optimum_voltage_table {
|
||||
unsigned int reference_uv;
|
||||
unsigned int optimized_uv;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct ti_opp_supply_data - OMAP specific opp supply data
|
||||
* @vdd_table: Optimized voltage mapping table
|
||||
* @num_vdd_table: number of entries in vdd_table
|
||||
* @vdd_absolute_max_voltage_uv: absolute maximum voltage in UV for the supply
|
||||
*/
|
||||
struct ti_opp_supply_data {
|
||||
struct ti_opp_supply_optimum_voltage_table *vdd_table;
|
||||
u32 num_vdd_table;
|
||||
u32 vdd_absolute_max_voltage_uv;
|
||||
};
|
||||
|
||||
static struct ti_opp_supply_data opp_data;
|
||||
|
||||
/**
|
||||
* struct ti_opp_supply_of_data - device tree match data
|
||||
* @flags: specific type of opp supply
|
||||
* @efuse_voltage_mask: mask required for efuse register representing voltage
|
||||
* @efuse_voltage_uv: Are the efuse entries in micro-volts? if not, assume
|
||||
* milli-volts.
|
||||
*/
|
||||
struct ti_opp_supply_of_data {
|
||||
#define OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE BIT(1)
|
||||
#define OPPDM_HAS_NO_ABB BIT(2)
|
||||
const u8 flags;
|
||||
const u32 efuse_voltage_mask;
|
||||
const bool efuse_voltage_uv;
|
||||
};
|
||||
|
||||
/**
|
||||
* _store_optimized_voltages() - store optimized voltages
|
||||
* @dev: ti opp supply device for which we need to store info
|
||||
* @data: data specific to the device
|
||||
*
|
||||
* Picks up efuse based optimized voltages for VDD unique per device and
|
||||
* stores it in internal data structure for use during transition requests.
|
||||
*
|
||||
* Return: If successful, 0, else appropriate error value.
|
||||
*/
|
||||
static int _store_optimized_voltages(struct device *dev,
|
||||
struct ti_opp_supply_data *data)
|
||||
{
|
||||
void __iomem *base;
|
||||
struct property *prop;
|
||||
struct resource *res;
|
||||
const __be32 *val;
|
||||
int proplen, i;
|
||||
int ret = 0;
|
||||
struct ti_opp_supply_optimum_voltage_table *table;
|
||||
const struct ti_opp_supply_of_data *of_data = dev_get_drvdata(dev);
|
||||
|
||||
/* pick up Efuse based voltages */
|
||||
res = platform_get_resource(to_platform_device(dev), IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(dev, "Unable to get IO resource\n");
|
||||
ret = -ENODEV;
|
||||
goto out_map;
|
||||
}
|
||||
|
||||
base = ioremap_nocache(res->start, resource_size(res));
|
||||
if (!base) {
|
||||
dev_err(dev, "Unable to map Efuse registers\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_map;
|
||||
}
|
||||
|
||||
/* Fetch efuse-settings. */
|
||||
prop = of_find_property(dev->of_node, "ti,efuse-settings", NULL);
|
||||
if (!prop) {
|
||||
dev_err(dev, "No 'ti,efuse-settings' property found\n");
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
proplen = prop->length / sizeof(int);
|
||||
data->num_vdd_table = proplen / 2;
|
||||
/* Verify for corrupted OPP entries in dt */
|
||||
if (data->num_vdd_table * 2 * sizeof(int) != prop->length) {
|
||||
dev_err(dev, "Invalid 'ti,efuse-settings'\n");
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(dev->of_node, "ti,absolute-max-voltage-uv",
|
||||
&data->vdd_absolute_max_voltage_uv);
|
||||
if (ret) {
|
||||
dev_err(dev, "ti,absolute-max-voltage-uv is missing\n");
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
table = kzalloc(sizeof(*data->vdd_table) *
|
||||
data->num_vdd_table, GFP_KERNEL);
|
||||
if (!table) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
data->vdd_table = table;
|
||||
|
||||
val = prop->value;
|
||||
for (i = 0; i < data->num_vdd_table; i++, table++) {
|
||||
u32 efuse_offset;
|
||||
u32 tmp;
|
||||
|
||||
table->reference_uv = be32_to_cpup(val++);
|
||||
efuse_offset = be32_to_cpup(val++);
|
||||
|
||||
tmp = readl(base + efuse_offset);
|
||||
tmp &= of_data->efuse_voltage_mask;
|
||||
tmp >>= __ffs(of_data->efuse_voltage_mask);
|
||||
|
||||
table->optimized_uv = of_data->efuse_voltage_uv ? tmp :
|
||||
tmp * 1000;
|
||||
|
||||
dev_dbg(dev, "[%d] efuse=0x%08x volt_table=%d vset=%d\n",
|
||||
i, efuse_offset, table->reference_uv,
|
||||
table->optimized_uv);
|
||||
|
||||
/*
|
||||
* Some older samples might not have optimized efuse
|
||||
* Use reference voltage for those - just add debug message
|
||||
* for them.
|
||||
*/
|
||||
if (!table->optimized_uv) {
|
||||
dev_dbg(dev, "[%d] efuse=0x%08x volt_table=%d:vset0\n",
|
||||
i, efuse_offset, table->reference_uv);
|
||||
table->optimized_uv = table->reference_uv;
|
||||
}
|
||||
}
|
||||
out:
|
||||
iounmap(base);
|
||||
out_map:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* _free_optimized_voltages() - free resources for optvoltages
|
||||
* @dev: device for which we need to free info
|
||||
* @data: data specific to the device
|
||||
*/
|
||||
static void _free_optimized_voltages(struct device *dev,
|
||||
struct ti_opp_supply_data *data)
|
||||
{
|
||||
kfree(data->vdd_table);
|
||||
data->vdd_table = NULL;
|
||||
data->num_vdd_table = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* _get_optimal_vdd_voltage() - Finds optimal voltage for the supply
|
||||
* @dev: device for which we need to find info
|
||||
* @data: data specific to the device
|
||||
* @reference_uv: reference voltage (OPP voltage) for which we need value
|
||||
*
|
||||
* Return: if a match is found, return optimized voltage, else return
|
||||
* reference_uv, also return reference_uv if no optimization is needed.
|
||||
*/
|
||||
static int _get_optimal_vdd_voltage(struct device *dev,
|
||||
struct ti_opp_supply_data *data,
|
||||
int reference_uv)
|
||||
{
|
||||
int i;
|
||||
struct ti_opp_supply_optimum_voltage_table *table;
|
||||
|
||||
if (!data->num_vdd_table)
|
||||
return reference_uv;
|
||||
|
||||
table = data->vdd_table;
|
||||
if (!table)
|
||||
return -EINVAL;
|
||||
|
||||
/* Find a exact match - this list is usually very small */
|
||||
for (i = 0; i < data->num_vdd_table; i++, table++)
|
||||
if (table->reference_uv == reference_uv)
|
||||
return table->optimized_uv;
|
||||
|
||||
/* IF things are screwed up, we'd make a mess on console.. ratelimit */
|
||||
dev_err_ratelimited(dev, "%s: Failed optimized voltage match for %d\n",
|
||||
__func__, reference_uv);
|
||||
return reference_uv;
|
||||
}
|
||||
|
||||
static int _opp_set_voltage(struct device *dev,
|
||||
struct dev_pm_opp_supply *supply,
|
||||
int new_target_uv, struct regulator *reg,
|
||||
char *reg_name)
|
||||
{
|
||||
int ret;
|
||||
unsigned long vdd_uv, uv_max;
|
||||
|
||||
if (new_target_uv)
|
||||
vdd_uv = new_target_uv;
|
||||
else
|
||||
vdd_uv = supply->u_volt;
|
||||
|
||||
/*
|
||||
* If we do have an absolute max voltage specified, then we should
|
||||
* use that voltage instead to allow for cases where the voltage rails
|
||||
* are ganged (example if we set the max for an opp as 1.12v, and
|
||||
* the absolute max is 1.5v, for another rail to get 1.25v, it cannot
|
||||
* be achieved if the regulator is constrainted to max of 1.12v, even
|
||||
* if it can function at 1.25v
|
||||
*/
|
||||
if (opp_data.vdd_absolute_max_voltage_uv)
|
||||
uv_max = opp_data.vdd_absolute_max_voltage_uv;
|
||||
else
|
||||
uv_max = supply->u_volt_max;
|
||||
|
||||
if (vdd_uv > uv_max ||
|
||||
vdd_uv < supply->u_volt_min ||
|
||||
supply->u_volt_min > uv_max) {
|
||||
dev_warn(dev,
|
||||
"Invalid range voltages [Min:%lu target:%lu Max:%lu]\n",
|
||||
supply->u_volt_min, vdd_uv, uv_max);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dev_dbg(dev, "%s scaling to %luuV[min %luuV max %luuV]\n", reg_name,
|
||||
vdd_uv, supply->u_volt_min,
|
||||
uv_max);
|
||||
|
||||
ret = regulator_set_voltage_triplet(reg,
|
||||
supply->u_volt_min,
|
||||
vdd_uv,
|
||||
uv_max);
|
||||
if (ret) {
|
||||
dev_err(dev, "%s failed for %luuV[min %luuV max %luuV]\n",
|
||||
reg_name, vdd_uv, supply->u_volt_min,
|
||||
uv_max);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ti_opp_supply_set_opp() - do the opp supply transition
|
||||
* @data: information on regulators and new and old opps provided by
|
||||
* opp core to use in transition
|
||||
*
|
||||
* Return: If successful, 0, else appropriate error value.
|
||||
*/
|
||||
int ti_opp_supply_set_opp(struct dev_pm_set_opp_data *data)
|
||||
{
|
||||
struct dev_pm_opp_supply *old_supply_vdd = &data->old_opp.supplies[0];
|
||||
struct dev_pm_opp_supply *old_supply_vbb = &data->old_opp.supplies[1];
|
||||
struct dev_pm_opp_supply *new_supply_vdd = &data->new_opp.supplies[0];
|
||||
struct dev_pm_opp_supply *new_supply_vbb = &data->new_opp.supplies[1];
|
||||
struct device *dev = data->dev;
|
||||
unsigned long old_freq = data->old_opp.rate, freq = data->new_opp.rate;
|
||||
struct clk *clk = data->clk;
|
||||
struct regulator *vdd_reg = data->regulators[0];
|
||||
struct regulator *vbb_reg = data->regulators[1];
|
||||
int vdd_uv;
|
||||
int ret;
|
||||
|
||||
vdd_uv = _get_optimal_vdd_voltage(dev, &opp_data,
|
||||
new_supply_vbb->u_volt);
|
||||
|
||||
/* Scaling up? Scale voltage before frequency */
|
||||
if (freq > old_freq) {
|
||||
ret = _opp_set_voltage(dev, new_supply_vdd, vdd_uv, vdd_reg,
|
||||
"vdd");
|
||||
if (ret)
|
||||
goto restore_voltage;
|
||||
|
||||
ret = _opp_set_voltage(dev, new_supply_vbb, 0, vbb_reg, "vbb");
|
||||
if (ret)
|
||||
goto restore_voltage;
|
||||
}
|
||||
|
||||
/* Change frequency */
|
||||
dev_dbg(dev, "%s: switching OPP: %lu Hz --> %lu Hz\n",
|
||||
__func__, old_freq, freq);
|
||||
|
||||
ret = clk_set_rate(clk, freq);
|
||||
if (ret) {
|
||||
dev_err(dev, "%s: failed to set clock rate: %d\n", __func__,
|
||||
ret);
|
||||
goto restore_voltage;
|
||||
}
|
||||
|
||||
/* Scaling down? Scale voltage after frequency */
|
||||
if (freq < old_freq) {
|
||||
ret = _opp_set_voltage(dev, new_supply_vbb, 0, vbb_reg, "vbb");
|
||||
if (ret)
|
||||
goto restore_freq;
|
||||
|
||||
ret = _opp_set_voltage(dev, new_supply_vdd, vdd_uv, vdd_reg,
|
||||
"vdd");
|
||||
if (ret)
|
||||
goto restore_freq;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
restore_freq:
|
||||
ret = clk_set_rate(clk, old_freq);
|
||||
if (ret)
|
||||
dev_err(dev, "%s: failed to restore old-freq (%lu Hz)\n",
|
||||
__func__, old_freq);
|
||||
restore_voltage:
|
||||
/* This shouldn't harm even if the voltages weren't updated earlier */
|
||||
if (old_supply_vdd->u_volt) {
|
||||
ret = _opp_set_voltage(dev, old_supply_vbb, 0, vbb_reg, "vbb");
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = _opp_set_voltage(dev, old_supply_vdd, 0, vdd_reg,
|
||||
"vdd");
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct ti_opp_supply_of_data omap_generic_of_data = {
|
||||
};
|
||||
|
||||
static const struct ti_opp_supply_of_data omap_omap5_of_data = {
|
||||
.flags = OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE,
|
||||
.efuse_voltage_mask = 0xFFF,
|
||||
.efuse_voltage_uv = false,
|
||||
};
|
||||
|
||||
static const struct ti_opp_supply_of_data omap_omap5core_of_data = {
|
||||
.flags = OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE | OPPDM_HAS_NO_ABB,
|
||||
.efuse_voltage_mask = 0xFFF,
|
||||
.efuse_voltage_uv = false,
|
||||
};
|
||||
|
||||
static const struct of_device_id ti_opp_supply_of_match[] = {
|
||||
{.compatible = "ti,omap-opp-supply", .data = &omap_generic_of_data},
|
||||
{.compatible = "ti,omap5-opp-supply", .data = &omap_omap5_of_data},
|
||||
{.compatible = "ti,omap5-core-opp-supply",
|
||||
.data = &omap_omap5core_of_data},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ti_opp_supply_of_match);
|
||||
|
||||
static int ti_opp_supply_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device *cpu_dev = get_cpu_device(0);
|
||||
const struct of_device_id *match;
|
||||
const struct ti_opp_supply_of_data *of_data;
|
||||
int ret = 0;
|
||||
|
||||
match = of_match_device(ti_opp_supply_of_match, dev);
|
||||
if (!match) {
|
||||
/* We do not expect this to happen */
|
||||
dev_err(dev, "%s: Unable to match device\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
if (!match->data) {
|
||||
/* Again, unlikely.. but mistakes do happen */
|
||||
dev_err(dev, "%s: Bad data in match\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
of_data = match->data;
|
||||
|
||||
dev_set_drvdata(dev, (void *)of_data);
|
||||
|
||||
/* If we need optimized voltage */
|
||||
if (of_data->flags & OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE) {
|
||||
ret = _store_optimized_voltages(dev, &opp_data);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = PTR_ERR_OR_ZERO(dev_pm_opp_register_set_opp_helper(cpu_dev,
|
||||
ti_opp_supply_set_opp));
|
||||
if (ret)
|
||||
_free_optimized_voltages(dev, &opp_data);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver ti_opp_supply_driver = {
|
||||
.probe = ti_opp_supply_probe,
|
||||
.driver = {
|
||||
.name = "ti_opp_supply",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(ti_opp_supply_of_match),
|
||||
},
|
||||
};
|
||||
module_platform_driver(ti_opp_supply_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Texas Instruments OMAP OPP Supply driver");
|
||||
MODULE_AUTHOR("Texas Instruments Inc.");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue