[POWERPC] Add 8641 Register space and IRQ definitions.
Signed-off-by: Jeff Brown <Jeff.Brown@freescale.com> Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>wifi-calibration
Jon Loeliger
Paul Mackerras
parent
b809b3e86f
commit
6b54340405
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/*
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* MPC86xx Internal Memory Map
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*
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* Author: Jeff Brown
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*
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* Copyright 2004 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __ASM_POWERPC_IMMAP_86XX_H__
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#define __ASM_POWERPC_IMMAP_86XX_H__
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#ifdef __KERNEL__
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/* Eventually this should define all the IO block registers in 86xx */
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/* PCI Registers */
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typedef struct ccsr_pci {
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uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */
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uint cfg_data; /* 0x.004 - PCI Configuration Data Register */
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uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
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char res1[3060];
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uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */
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uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */
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uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */
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char res2[4];
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uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */
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char res3[12];
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uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */
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uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */
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uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */
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char res4[4];
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uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */
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char res5[12];
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uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */
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uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */
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uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */
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char res6[4];
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uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */
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char res7[12];
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uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */
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uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */
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uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */
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char res8[4];
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uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */
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char res9[12];
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uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */
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uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */
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uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */
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char res10[4];
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uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */
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char res11[268];
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uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */
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char res12[4];
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uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */
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uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */
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uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */
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char res13[12];
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uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */
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char res14[4];
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uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */
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uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */
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uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */
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char res15[12];
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uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */
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char res16[4];
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uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */
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char res17[4];
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uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */
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char res18[12];
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uint err_dr; /* 0x.e00 - PCI Error Detect Register */
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uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */
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uint err_en; /* 0x.e08 - PCI Error Enable Register */
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uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */
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uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */
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uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */
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uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */
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uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */
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uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */
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uint pci_timr; /* 0x.e24 - PCI Timer Register */
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char res19[472];
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} ccsr_pci_t;
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/* PCI Express Registers */
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typedef struct ccsr_pex {
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uint pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
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uint pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
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char res1[4];
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uint pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
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uint pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
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char res2[12];
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uint pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
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uint pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
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uint pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
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uint pex_pmcr; /* 0x.02c - PCI Express power management command register */
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char res3[3024];
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uint pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
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uint pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
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char res4[8];
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uint pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
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char res5[12];
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uint pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
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uint pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
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uint pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
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char res6[4];
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uint pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
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char res7[12];
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uint pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
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uint pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
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uint pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
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char res8[4];
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uint pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
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char res9[12];
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uint pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
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uint pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
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uint pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
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char res10[4];
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uint pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
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char res11[12];
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uint pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
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uint pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
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uint pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
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char res12[4];
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uint pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
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char res13[12];
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char res14[256];
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uint pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
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char res15[4];
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uint pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
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uint pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
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uint pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
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char res16[12];
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uint pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
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char res17[4];
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uint pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
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uint pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
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uint pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
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char res18[12];
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uint pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
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char res19[4];
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uint pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
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uint pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
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uint pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
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char res20[12];
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uint pex_err_dr; /* 0x.e00 - PCI Express error detect register */
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char res21[4];
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uint pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
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char res22[4];
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uint pex_err_disr; /* 0x.e10 - PCI Express error disable register */
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char res23[12];
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uint pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
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char res24[4];
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uint pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
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uint pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
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uint pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
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uint pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
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} ccsr_pex_t;
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/* Global Utility Registers */
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typedef struct ccsr_guts {
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uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
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uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
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uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
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uint pordevsr; /* 0x.000c - POR I/O Device Status Register */
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uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
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char res1[12];
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uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */
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char res2[12];
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uint gpiocr; /* 0x.0030 - GPIO Control Register */
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char res3[12];
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uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
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char res4[12];
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uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */
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char res5[12];
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uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
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char res6[12];
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uint devdisr; /* 0x.0070 - Device Disable Control */
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char res7[12];
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uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
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char res8[12];
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uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */
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char res9[12];
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uint pvr; /* 0x.00a0 - Processor Version Register */
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uint svr; /* 0x.00a4 - System Version Register */
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char res10[3416];
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uint clkocr; /* 0x.0e00 - Clock Out Select Register */
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char res11[12];
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uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
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char res12[12];
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uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
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char res13[61916];
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} ccsr_guts_t;
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#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
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#endif /* __KERNEL__ */
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@ -348,6 +348,92 @@ extern u64 ppc64_interrupt_controller;
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#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
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#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
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#elif defined(CONFIG_PPC_86xx)
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#include <asm/mpc86xx.h>
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#define NR_EPIC_INTS 48
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#ifndef NR_8259_INTS
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#define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */
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#endif
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#define NUM_8259_INTERRUPTS NR_8259_INTS
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#ifndef I8259_OFFSET
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#define I8259_OFFSET 0
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#endif
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#define NR_IRQS 256
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/* Internal IRQs on MPC86xx OpenPIC */
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#ifndef MPC86xx_OPENPIC_IRQ_OFFSET
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#define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
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#endif
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/* The 48 internal sources */
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#define MPC86xx_IRQ_NULL ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_MCM ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_DDR ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_LBC ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_DMA0 ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_DMA1 ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_DMA2 ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_DMA3 ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET)
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/* no 10,11 */
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#define MPC86xx_IRQ_UART2 (12 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_TSEC1_TX (13 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_TSEC1_RX (14 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_TSEC3_TX (15 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_TSEC3_RX (16 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_TSEC2_TX (19 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_TSEC2_RX (20 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_TSEC4_TX (21 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_TSEC4_RX (22 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET)
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/* no 25 */
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#define MPC86xx_IRQ_UART1 (26 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_IIC (27 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_PERFMON (28 + MPC86xx_OPENPIC_IRQ_OFFSET)
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/* no 29,30,31 */
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#define MPC86xx_IRQ_SRIO_ERROR (32 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_SRIO_IN_BELL (34 + MPC86xx_OPENPIC_IRQ_OFFSET)
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/* no 35,36 */
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#define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_SRIO_IN_MSG1 (38 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_SRIO_IN_MSG2 (40 + MPC86xx_OPENPIC_IRQ_OFFSET)
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/* The 12 external interrupt lines */
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#define MPC86xx_IRQ_EXT_BASE 48
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#define MPC86xx_IRQ_EXT0 (0 + MPC86xx_IRQ_EXT_BASE \
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+ MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_EXT1 (1 + MPC86xx_IRQ_EXT_BASE \
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+ MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_EXT2 (2 + MPC86xx_IRQ_EXT_BASE \
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+ MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_EXT3 (3 + MPC86xx_IRQ_EXT_BASE \
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+ MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_EXT4 (4 + MPC86xx_IRQ_EXT_BASE \
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+ MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_EXT5 (5 + MPC86xx_IRQ_EXT_BASE \
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+ MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_EXT6 (6 + MPC86xx_IRQ_EXT_BASE \
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+ MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_EXT7 (7 + MPC86xx_IRQ_EXT_BASE \
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+ MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_EXT8 (8 + MPC86xx_IRQ_EXT_BASE \
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+ MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_EXT9 (9 + MPC86xx_IRQ_EXT_BASE \
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+ MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_EXT10 (10 + MPC86xx_IRQ_EXT_BASE \
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+ MPC86xx_OPENPIC_IRQ_OFFSET)
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#define MPC86xx_IRQ_EXT11 (11 + MPC86xx_IRQ_EXT_BASE \
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+ MPC86xx_OPENPIC_IRQ_OFFSET)
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#else /* CONFIG_40x + CONFIG_8xx */
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/*
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* this is the # irq's for all ppc arch's (pmac/chrp/prep)
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@ -0,0 +1,47 @@
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/*
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* MPC86xx definitions
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*
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* Author: Jeff Brown
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*
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* Copyright 2004 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_POWERPC_MPC86xx_H__
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#define __ASM_POWERPC_MPC86xx_H__
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#include <linux/config.h>
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#include <asm/mmu.h>
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#ifdef CONFIG_PPC_86xx
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#ifdef CONFIG_MPC8641_HPCN
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#include <platforms/86xx/mpc8641_hpcn.h>
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#endif
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#define _IO_BASE isa_io_base
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#define _ISA_MEM_BASE isa_mem_base
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#ifdef CONFIG_PCI
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#define PCI_DRAM_OFFSET pci_dram_offset
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#else
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#define PCI_DRAM_OFFSET 0
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#endif
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#define CPU0_BOOT_RELEASE 0x01000000
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#define CPU1_BOOT_RELEASE 0x02000000
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#define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE)
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#define MCM_PORT_CONFIG_OFFSET 0x1010
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/* Offset from CCSRBAR */
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#define MPC86xx_OPENPIC_OFFSET (0x40000)
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#define MPC86xx_MCM_OFFSET (0x00000)
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#define MPC86xx_MCM_SIZE (0x02000)
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#endif /* CONFIG_PPC_86xx */
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#endif /* __ASM_POWERPC_MPC86xx_H__ */
|
||||
#endif /* __KERNEL__ */
|
||||
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Reference in New Issue