clk: mmp: add mmp specific clocks
add mmp specific clocks including apbc cloks, apmu clocks, and pll2, fraction clocks Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Chao Xie
Mike Turquette
parent
f9a6aa4303
commit
6b63f02318
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@ -11,6 +11,9 @@ obj-$(CONFIG_PLAT_SPEAR) += spear/
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obj-$(CONFIG_ARCH_U300) += clk-u300.o
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obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
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obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o
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ifeq ($(CONFIG_COMMON_CLK), y)
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obj-$(CONFIG_ARCH_MMP) += mmp/
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endif
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# Chip specific
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obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
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5
drivers/clk/mmp/Makefile
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5
drivers/clk/mmp/Makefile
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@ -0,0 +1,5 @@
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#
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# Makefile for mmp specific clk
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#
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obj-y += clk-apbc.o clk-apmu.o clk-frac.o
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152
drivers/clk/mmp/clk-apbc.c
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152
drivers/clk/mmp/clk-apbc.c
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@ -0,0 +1,152 @@
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/*
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* mmp APB clock operation source file
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*
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* Copyright (C) 2012 Marvell
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* Chao Xie <xiechao.mail@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include "clk.h"
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/* Common APB clock register bit definitions */
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#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
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#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
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#define APBC_RST (1 << 2) /* Reset Generation */
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#define APBC_POWER (1 << 7) /* Reset Generation */
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#define to_clk_apbc(hw) container_of(hw, struct clk_apbc, hw)
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struct clk_apbc {
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struct clk_hw hw;
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void __iomem *base;
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unsigned int delay;
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unsigned int flags;
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spinlock_t *lock;
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};
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static int clk_apbc_prepare(struct clk_hw *hw)
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{
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struct clk_apbc *apbc = to_clk_apbc(hw);
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unsigned int data;
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unsigned long flags = 0;
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/*
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* It may share same register as MUX clock,
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* and it will impact FNCLK enable. Spinlock is needed
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*/
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if (apbc->lock)
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spin_lock_irqsave(apbc->lock, flags);
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data = readl_relaxed(apbc->base);
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if (apbc->flags & APBC_POWER_CTRL)
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data |= APBC_POWER;
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data |= APBC_FNCLK;
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writel_relaxed(data, apbc->base);
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if (apbc->lock)
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spin_unlock_irqrestore(apbc->lock, flags);
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udelay(apbc->delay);
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if (apbc->lock)
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spin_lock_irqsave(apbc->lock, flags);
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data = readl_relaxed(apbc->base);
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data |= APBC_APBCLK;
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writel_relaxed(data, apbc->base);
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if (apbc->lock)
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spin_unlock_irqrestore(apbc->lock, flags);
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udelay(apbc->delay);
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if (!(apbc->flags & APBC_NO_BUS_CTRL)) {
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if (apbc->lock)
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spin_lock_irqsave(apbc->lock, flags);
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data = readl_relaxed(apbc->base);
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data &= ~APBC_RST;
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writel_relaxed(data, apbc->base);
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if (apbc->lock)
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spin_unlock_irqrestore(apbc->lock, flags);
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}
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return 0;
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}
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static void clk_apbc_unprepare(struct clk_hw *hw)
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{
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struct clk_apbc *apbc = to_clk_apbc(hw);
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unsigned long data;
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unsigned long flags = 0;
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if (apbc->lock)
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spin_lock_irqsave(apbc->lock, flags);
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data = readl_relaxed(apbc->base);
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if (apbc->flags & APBC_POWER_CTRL)
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data &= ~APBC_POWER;
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data &= ~APBC_FNCLK;
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writel_relaxed(data, apbc->base);
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if (apbc->lock)
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spin_unlock_irqrestore(apbc->lock, flags);
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udelay(10);
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if (apbc->lock)
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spin_lock_irqsave(apbc->lock, flags);
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data = readl_relaxed(apbc->base);
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data &= ~APBC_APBCLK;
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writel_relaxed(data, apbc->base);
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if (apbc->lock)
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spin_unlock_irqrestore(apbc->lock, flags);
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}
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struct clk_ops clk_apbc_ops = {
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.prepare = clk_apbc_prepare,
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.unprepare = clk_apbc_unprepare,
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};
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struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name,
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void __iomem *base, unsigned int delay,
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unsigned int apbc_flags, spinlock_t *lock)
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{
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struct clk_apbc *apbc;
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struct clk *clk;
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struct clk_init_data init;
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apbc = kzalloc(sizeof(*apbc), GFP_KERNEL);
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if (!apbc)
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return NULL;
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init.name = name;
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init.ops = &clk_apbc_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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apbc->base = base;
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apbc->delay = delay;
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apbc->flags = apbc_flags;
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apbc->lock = lock;
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apbc->hw.init = &init;
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clk = clk_register(NULL, &apbc->hw);
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if (IS_ERR(clk))
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kfree(apbc);
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return clk;
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}
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97
drivers/clk/mmp/clk-apmu.c
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97
drivers/clk/mmp/clk-apmu.c
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@ -0,0 +1,97 @@
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/*
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* mmp AXI peripharal clock operation source file
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*
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* Copyright (C) 2012 Marvell
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* Chao Xie <xiechao.mail@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include "clk.h"
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#define to_clk_apmu(clk) (container_of(clk, struct clk_apmu, clk))
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struct clk_apmu {
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struct clk_hw hw;
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void __iomem *base;
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u32 rst_mask;
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u32 enable_mask;
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spinlock_t *lock;
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};
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static int clk_apmu_enable(struct clk_hw *hw)
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{
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struct clk_apmu *apmu = to_clk_apmu(hw);
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unsigned long data;
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unsigned long flags = 0;
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if (apmu->lock)
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spin_lock_irqsave(apmu->lock, flags);
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data = readl_relaxed(apmu->base) | apmu->enable_mask;
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writel_relaxed(data, apmu->base);
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if (apmu->lock)
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spin_unlock_irqrestore(apmu->lock, flags);
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return 0;
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}
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static void clk_apmu_disable(struct clk_hw *hw)
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{
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struct clk_apmu *apmu = to_clk_apmu(hw);
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unsigned long data;
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unsigned long flags = 0;
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if (apmu->lock)
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spin_lock_irqsave(apmu->lock, flags);
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data = readl_relaxed(apmu->base) & ~apmu->enable_mask;
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writel_relaxed(data, apmu->base);
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if (apmu->lock)
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spin_unlock_irqrestore(apmu->lock, flags);
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}
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struct clk_ops clk_apmu_ops = {
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.enable = clk_apmu_enable,
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.disable = clk_apmu_disable,
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};
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struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name,
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void __iomem *base, u32 enable_mask, spinlock_t *lock)
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{
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struct clk_apmu *apmu;
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struct clk *clk;
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struct clk_init_data init;
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apmu = kzalloc(sizeof(*apmu), GFP_KERNEL);
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if (!apmu)
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return NULL;
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init.name = name;
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init.ops = &clk_apmu_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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apmu->base = base;
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apmu->enable_mask = enable_mask;
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apmu->lock = lock;
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apmu->hw.init = &init;
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clk = clk_register(NULL, &apmu->hw);
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if (IS_ERR(clk))
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kfree(apmu);
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return clk;
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}
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153
drivers/clk/mmp/clk-frac.c
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153
drivers/clk/mmp/clk-frac.c
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@ -0,0 +1,153 @@
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/*
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* mmp factor clock operation source file
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*
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* Copyright (C) 2012 Marvell
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* Chao Xie <xiechao.mail@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include "clk.h"
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/*
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* It is M/N clock
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*
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* Fout from synthesizer can be given from two equations:
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* numerator/denominator = Fin / (Fout * factor)
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*/
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#define to_clk_factor(hw) container_of(hw, struct clk_factor, hw)
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struct clk_factor {
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struct clk_hw hw;
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void __iomem *base;
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struct clk_factor_masks *masks;
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struct clk_factor_tbl *ftbl;
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unsigned int ftbl_cnt;
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};
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static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long *prate)
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{
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struct clk_factor *factor = to_clk_factor(hw);
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unsigned long rate = 0, prev_rate;
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int i;
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for (i = 0; i < factor->ftbl_cnt; i++) {
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prev_rate = rate;
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rate = (((*prate / 10000) * factor->ftbl[i].num) /
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(factor->ftbl[i].den * factor->masks->factor)) * 10000;
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if (rate > drate)
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break;
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}
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if (i == 0)
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return rate;
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else
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return prev_rate;
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}
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static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_factor *factor = to_clk_factor(hw);
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struct clk_factor_masks *masks = factor->masks;
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unsigned int val, num, den;
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val = readl_relaxed(factor->base);
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/* calculate numerator */
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num = (val >> masks->num_shift) & masks->num_mask;
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/* calculate denominator */
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den = (val >> masks->den_shift) & masks->num_mask;
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if (!den)
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return 0;
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return (((parent_rate / 10000) * den) /
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(num * factor->masks->factor)) * 10000;
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}
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/* Configures new clock rate*/
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static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long prate)
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{
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struct clk_factor *factor = to_clk_factor(hw);
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struct clk_factor_masks *masks = factor->masks;
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int i;
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unsigned long val;
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unsigned long prev_rate, rate = 0;
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for (i = 0; i < factor->ftbl_cnt; i++) {
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prev_rate = rate;
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rate = (((prate / 10000) * factor->ftbl[i].num) /
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(factor->ftbl[i].den * factor->masks->factor)) * 10000;
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if (rate > drate)
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break;
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}
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if (i > 0)
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i--;
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val = readl_relaxed(factor->base);
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val &= ~(masks->num_mask << masks->num_shift);
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val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift;
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val &= ~(masks->den_mask << masks->den_shift);
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val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift;
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writel_relaxed(val, factor->base);
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return 0;
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}
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static struct clk_ops clk_factor_ops = {
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.recalc_rate = clk_factor_recalc_rate,
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.round_rate = clk_factor_round_rate,
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.set_rate = clk_factor_set_rate,
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};
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struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
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unsigned long flags, void __iomem *base,
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struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl,
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unsigned int ftbl_cnt)
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{
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struct clk_factor *factor;
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struct clk_init_data init;
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struct clk *clk;
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if (!masks) {
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pr_err("%s: must pass a clk_factor_mask\n", __func__);
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return ERR_PTR(-EINVAL);
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}
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factor = kzalloc(sizeof(*factor), GFP_KERNEL);
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if (!factor) {
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pr_err("%s: could not allocate factor clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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/* struct clk_aux assignments */
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factor->base = base;
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factor->masks = masks;
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factor->ftbl = ftbl;
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factor->ftbl_cnt = ftbl_cnt;
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factor->hw.init = &init;
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init.name = name;
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init.ops = &clk_factor_ops;
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init.flags = flags;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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clk = clk_register(NULL, &factor->hw);
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if (IS_ERR_OR_NULL(clk))
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kfree(factor);
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return clk;
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}
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35
drivers/clk/mmp/clk.h
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35
drivers/clk/mmp/clk.h
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@ -0,0 +1,35 @@
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#ifndef __MACH_MMP_CLK_H
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#define __MACH_MMP_CLK_H
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#define APBC_NO_BUS_CTRL BIT(0)
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#define APBC_POWER_CTRL BIT(1)
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struct clk_factor_masks {
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unsigned int factor;
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unsigned int num_mask;
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unsigned int den_mask;
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unsigned int num_shift;
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unsigned int den_shift;
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};
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struct clk_factor_tbl {
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unsigned int num;
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unsigned int den;
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};
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extern struct clk *mmp_clk_register_pll2(const char *name,
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const char *parent_name, unsigned long flags);
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extern struct clk *mmp_clk_register_apbc(const char *name,
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const char *parent_name, void __iomem *base,
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unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
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extern struct clk *mmp_clk_register_apmu(const char *name,
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const char *parent_name, void __iomem *base, u32 enable_mask,
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spinlock_t *lock);
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extern struct clk *mmp_clk_register_factor(const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *base, struct clk_factor_masks *masks,
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struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt);
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#endif
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