crypto: caam - add support for LS1021A
LS1021A is a QorIQ SoC having little endian CAAM. There are a few differences b/w QorIQ and i.MX from CAAM perspective: 1. i.MX platforms are somewhat special wrt. 64-bit registers: -big endian format at 64-bit level: MSW at address+0 and LSW at address+4 -little endian format at 32-bit level (within MSW and LSW) and thus need special handling. 2. No CCM (clock controller module) for QorIQ. No CAAM clocks to enable / disable. A new Kconfig option - CRYPTO_DEV_FSL_CAAM_LE - is added to indicate CAAM is little endian (*). It is hidden from the user (to avoid misconfiguration); when adding support for a new platform with LE CAAM, either the Kconfig needs to be updated or the corresponding defconfig needs to indicate that CAAM is LE. (*) Using a DT property to provide CAAM endianness would not allow for the ifdeffery. In order to keep changes to a minimum, the following changes are postponed: -endianness fix of the last word in the S/G (rsvd2, bpid, offset), fields are always 0 anyway; -S/G format fix for i.MX7 (yes, i.MX7 support was not added yet, but still...) Signed-off-by: Horia Geant? <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -112,6 +112,14 @@ config CRYPTO_DEV_FSL_CAAM_RNG_API
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To compile this as a module, choose M here: the module
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will be called caamrng.
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config CRYPTO_DEV_FSL_CAAM_IMX
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def_bool SOC_IMX6 || SOC_IMX7D
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depends on CRYPTO_DEV_FSL_CAAM
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config CRYPTO_DEV_FSL_CAAM_LE
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def_bool CRYPTO_DEV_FSL_CAAM_IMX || SOC_LS1021A
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depends on CRYPTO_DEV_FSL_CAAM
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config CRYPTO_DEV_FSL_CAAM_DEBUG
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bool "Enable debug output in CAAM driver"
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depends on CRYPTO_DEV_FSL_CAAM
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@ -16,10 +16,10 @@
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#include "error.h"
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/*
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* ARM targets tend to have clock control subsystems that can
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* i.MX targets tend to have clock control subsystems that can
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* enable/disable clocking to our device.
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*/
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#ifdef CONFIG_ARM
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#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
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static inline struct clk *caam_drv_identify_clk(struct device *dev,
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char *clk_name)
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{
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@ -23,12 +23,12 @@
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#define SEC4_SG_OFFS_MASK 0x00001fff
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struct sec4_sg_entry {
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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dma_addr_t ptr;
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#else
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#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
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u32 rsvd1;
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dma_addr_t ptr;
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#endif
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#else
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u64 ptr;
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#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_IMX */
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u32 len;
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u8 rsvd2;
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u8 buf_pool_id;
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@ -108,20 +108,31 @@
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/*
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* The only users of these wr/rd_reg64 functions is the Job Ring (JR).
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* The DMA address registers in the JR are a pair of 32-bit registers.
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* The layout is:
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* The DMA address registers in the JR are handled differently depending on
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* platform:
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*
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* 1. All BE CAAM platforms and i.MX platforms (LE CAAM):
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*
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* base + 0x0000 : most-significant 32 bits
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* base + 0x0004 : least-significant 32 bits
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*
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* The 32-bit version of this core therefore has to write to base + 0x0004
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* to set the 32-bit wide DMA address. This seems to be independent of the
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* endianness of the written/read data.
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* to set the 32-bit wide DMA address.
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*
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* 2. All other LE CAAM platforms (LS1021A etc.)
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* base + 0x0000 : least-significant 32 bits
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* base + 0x0004 : most-significant 32 bits
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*/
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#ifndef CONFIG_64BIT
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#if !defined(CONFIG_CRYPTO_DEV_FSL_CAAM_LE) || \
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defined(CONFIG_CRYPTO_DEV_FSL_CAAM_IMX)
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#define REG64_MS32(reg) ((u32 __iomem *)(reg))
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#define REG64_LS32(reg) ((u32 __iomem *)(reg) + 1)
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#else
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#define REG64_MS32(reg) ((u32 __iomem *)(reg) + 1)
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#define REG64_LS32(reg) ((u32 __iomem *)(reg))
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#endif
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static inline void wr_reg64(u64 __iomem *reg, u64 data)
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{
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