ASoC: fsl_ssi: Don't try to round-up for PM divisor calculation
According to i.MX6 Series Reference Manual, the formula to calculate the sys clock is sysclk rate = bclk rate * (div2 + 1) * (7 * psr + 1) * (pm + 1) * 2 Commitaafa85e71a
("ASoC: fsl_ssi: Add DAI master mode support for SSI on i.MX series") added the divisor calculation which relies on the clk_round_rate(). However, at that time, clk_round_rate() didn't provide closest clock rates for some cases because it might not use a correct rounding policy. So using the original formula (pm + 1) for PM divisor was not able to give us a desired clock rate. And then we used (pm + 2) to do the trick. However, the clk-divider driver has been refined a lot since commitb11d282dbe
("clk: divider: fix rate calculation for fractional rates") Now using (pm + 2) trick would result an incorrect clock rate. So this patch fixes the problem by removing the useless trick. Reported-by: Stephane Cerveau <scerveau@voxtok.com> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -603,7 +603,7 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
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factor = (div2 + 1) * (7 * psr + 1) * 2;
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for (i = 0; i < 255; i++) {
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tmprate = freq * factor * (i + 2);
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tmprate = freq * factor * (i + 1);
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if (baudclk_is_used)
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clkrate = clk_get_rate(ssi_private->baudclk);
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