clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks
commit0f6f9302b8
upstream. The audio module clocks are supposed to be set according to the sample rate of the audio stream. The audio PLL provides the clock signal for these module clocks, and only it is freely tunable. Set CLK_SET_RATE_PARENT for the audio module clocks so their users can properly tune the clock rate. Fixes:0577e4853b
("clk: sunxi-ng: Add H3 clocks") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -394,16 +394,16 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
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static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
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"pll-audio-2x", "pll-audio" };
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static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
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0x0b0, 16, 2, BIT(31), 0);
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0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
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0x0b4, 16, 2, BIT(31), 0);
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0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
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0x0b8, 16, 2, BIT(31), 0);
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0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
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0x0c0, 0, 4, BIT(31), 0);
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0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
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0x0cc, BIT(8), 0);
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@ -466,7 +466,7 @@ static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
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0x13c, 16, 3, BIT(31), 0);
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static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
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0x140, BIT(31), 0);
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0x140, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
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0x144, BIT(31), 0);
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