Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle: "Fixes for a number of small glitches in various corners of the MIPS tree. No particular areas is standing out. With this applied all MIPS defconfigs are building fine. No merge conflicts are expected." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: Delete definition of SA_RESTORER. MIPS: Fix ISA level which causes secondary cache init bypassing and more MIPS: Fix build error cavium-octeon without CONFIG_SMP MIPS: Kconfig: Rename SNIPROM too MIPS: Alchemy: Fix typo "CONFIG_DEBUG_PCI" MIPS: Unbreak function tracer for 64-bit kernel.
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commit
6cfa92382e
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@ -657,7 +657,7 @@ config SNI_RM
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bool "SNI RM200/300/400"
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select FW_ARC if CPU_LITTLE_ENDIAN
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select FW_ARC32 if CPU_LITTLE_ENDIAN
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select SNIPROM if CPU_BIG_ENDIAN
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select FW_SNIPROM if CPU_BIG_ENDIAN
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select ARCH_MAY_HAVE_PC_FDC
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select BOOT_ELF32
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select CEVT_R4K
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@ -1144,7 +1144,7 @@ config DEFAULT_SGI_PARTITION
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config FW_ARC32
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bool
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config SNIPROM
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config FW_SNIPROM
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bool
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config BOOT_ELF32
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@ -174,7 +174,10 @@ static int octeon_kexec_prepare(struct kimage *image)
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static void octeon_generic_shutdown(void)
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{
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int cpu, i;
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int i;
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#ifdef CONFIG_SMP
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int cpu;
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#endif
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struct cvmx_bootmem_desc *bootmem_desc;
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void *named_block_array_ptr;
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@ -72,6 +72,12 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */
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*
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* SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
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* Unix names RESETHAND and NODEFER respectively.
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*
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* SA_RESTORER used to be defined as 0x04000000 but only the O32 ABI ever
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* supported its use and no libc was using it, so the entire sa-restorer
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* functionality was removed with lmo commit 39bffc12c3580ab for 2.5.48
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* retaining only the SA_RESTORER definition as a reminder to avoid
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* accidental reuse of the mask bit.
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*/
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#define SA_ONSTACK 0x08000000
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#define SA_RESETHAND 0x80000000
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@ -84,8 +90,6 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */
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#define SA_NOMASK SA_NODEFER
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#define SA_ONESHOT SA_RESETHAND
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#define SA_RESTORER 0x04000000 /* Only for o32 */
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#define MINSIGSTKSZ 2048
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#define SIGSTKSZ 8192
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@ -1227,10 +1227,8 @@ __cpuinit void cpu_probe(void)
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if (c->options & MIPS_CPU_FPU) {
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c->fpu_id = cpu_get_fpu_id();
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if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
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c->isa_level == MIPS_CPU_ISA_M32R2 ||
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c->isa_level == MIPS_CPU_ISA_M64R1 ||
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c->isa_level == MIPS_CPU_ISA_M64R2) {
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if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
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MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
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if (c->fpu_id & MIPS_FPIR_3D)
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c->ases |= MIPS_ASE_MIPS3D;
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}
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@ -46,10 +46,9 @@
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PTR_L a5, PT_R9(sp)
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PTR_L a6, PT_R10(sp)
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PTR_L a7, PT_R11(sp)
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#else
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PTR_ADDIU sp, PT_SIZE
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#endif
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.endm
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PTR_ADDIU sp, PT_SIZE
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.endm
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.macro RETURN_BACK
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jr ra
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@ -68,7 +67,11 @@ NESTED(ftrace_caller, PT_SIZE, ra)
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.globl _mcount
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_mcount:
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b ftrace_stub
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addiu sp,sp,8
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#ifdef CONFIG_32BIT
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addiu sp,sp,8
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#else
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nop
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#endif
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/* When tracing is activated, it calls ftrace_caller+8 (aka here) */
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lw t1, function_trace_stop
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@ -1571,7 +1571,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
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#ifdef CONFIG_64BIT
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status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
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#endif
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if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
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if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
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status_set |= ST0_XX;
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if (cpu_has_dsp)
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status_set |= ST0_MX;
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@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void)
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return;
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default:
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if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
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c->isa_level == MIPS_CPU_ISA_M32R2 ||
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c->isa_level == MIPS_CPU_ISA_M64R1 ||
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c->isa_level == MIPS_CPU_ISA_M64R2) {
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if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
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MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
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#ifdef CONFIG_MIPS_CPU_SCACHE
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if (mips_sc_init ()) {
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scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
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@ -98,10 +98,8 @@ static inline int __init mips_sc_probe(void)
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c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
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/* Ignore anything but MIPSxx processors */
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if (c->isa_level != MIPS_CPU_ISA_M32R1 &&
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c->isa_level != MIPS_CPU_ISA_M32R2 &&
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c->isa_level != MIPS_CPU_ISA_M64R1 &&
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c->isa_level != MIPS_CPU_ISA_M64R2)
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if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
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MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
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return 0;
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/* Does this MIPS32/MIPS64 CPU have a config2 register? */
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@ -19,7 +19,7 @@
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/tlbmisc.h>
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#ifdef CONFIG_DEBUG_PCI
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#ifdef CONFIG_PCI_DEBUG
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#define DBG(x...) printk(KERN_DEBUG x)
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#else
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#define DBG(x...) do {} while (0)
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@ -162,7 +162,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
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if (status & (1 << 29)) {
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*data = 0xffffffff;
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error = -1;
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DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d",
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DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n",
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access_type, bus->number, device);
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} else if ((status >> 28) & 0xf) {
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DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
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