ARM: dts: sun6i: Add device nodes for first display pipeline
The A31 has 2 parallel display pipelines, which can be intermixed. However the driver currently only supports one of them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -231,6 +231,11 @@
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de: display-engine {
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compatible = "allwinner,sun6i-a31-display-engine";
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allwinner,pipelines = <&fe0>;
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};
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soc@01c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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@ -246,6 +251,44 @@
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#dma-cells = <1>;
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};
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tcon0: lcd-controller@01c0c000 {
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compatible = "allwinner,sun6i-a31-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&ccu RST_AHB1_LCD0>;
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reset-names = "lcd";
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clocks = <&ccu CLK_AHB1_LCD0>,
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<&ccu CLK_LCD0_CH0>,
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<&ccu CLK_LCD0_CH1>;
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clock-names = "ahb",
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"tcon-ch0",
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"tcon-ch1";
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clock-output-names = "tcon0-pixel-clock";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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tcon0_in_drc0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drc0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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};
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};
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c0f000 0x1000>;
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@ -799,6 +842,115 @@
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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fe0: display-frontend@01e00000 {
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compatible = "allwinner,sun6i-a31-display-frontend";
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reg = <0x01e00000 0x20000>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
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<&ccu CLK_DRAM_FE0>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_AHB1_FE0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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fe0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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fe0_out_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_in_fe0>;
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};
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};
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};
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};
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be0: display-backend@01e60000 {
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compatible = "allwinner,sun6i-a31-display-backend";
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reg = <0x01e60000 0x10000>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
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<&ccu CLK_DRAM_BE0>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_AHB1_BE0>;
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assigned-clocks = <&ccu CLK_BE0>;
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assigned-clock-rates = <300000000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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be0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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be0_in_fe0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&fe0_out_be0>;
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};
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};
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be0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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be0_out_drc0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&drc0_in_be0>;
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};
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};
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};
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};
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drc0: drc@01e70000 {
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compatible = "allwinner,sun6i-a31-drc";
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reg = <0x01e70000 0x10000>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
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<&ccu CLK_DRAM_DRC0>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&ccu RST_AHB1_DRC0>;
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assigned-clocks = <&ccu CLK_IEP_DRC0>;
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assigned-clock-rates = <300000000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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drc0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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drc0_in_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_out_drc0>;
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};
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};
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drc0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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drc0_out_tcon0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_in_drc0>;
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};
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};
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};
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};
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rtc: rtc@01f00000 {
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compatible = "allwinner,sun6i-a31-rtc";
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reg = <0x01f00000 0x54>;
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@ -48,6 +48,14 @@
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#include "sun6i-a31.dtsi"
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&de {
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compatible = "allwinner,sun6i-a31s-display-engine";
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};
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&pio {
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compatible = "allwinner,sun6i-a31s-pinctrl";
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};
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&tcon0 {
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compatible = "allwinner,sun6i-a31s-tcon";
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};
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