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usb: phy: samsung: Add support HSIC on Exynos4X12

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This patch adds to enable High Speed Inter Chip on Exynos4X12. Both channels
are controlled by usbphy driver based on the patch series of usbphy driver
submitted by Tomasz Figa.

[1] https://patchwork.kernel.org/patch/2576121
[2] https://patchwork.kernel.org/patch/2576131
[3] https://patchwork.kernel.org/patch/2576141
[4] https://patchwork.kernel.org/patch/2576151
[5] https://patchwork.kernel.org/patch/2576161
[6] https://patchwork.kernel.org/patch/2576171

Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Dongjin Kim 2013-05-22 02:01:46 +09:00 committed by Felipe Balbi
parent 7a22cc9709
commit 6d3d61f821
3 changed files with 26 additions and 2 deletions
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5
drivers/usb/phy/phy-samsung-usb.c
View file

@ -100,6 +100,11 @@ void samsung_usbphy_set_isolation_4210(struct samsung_usbphy *sphy, bool on)
reg_val |= en_mask;
writel(reg_val, reg);
if (sphy->drv_data->cpu_type == TYPE_EXYNOS4X12) {
writel(reg_val, sphy->pmuregs + EXYNOS4X12_PHY_HSIC_CTRL0);
writel(reg_val, sphy->pmuregs + EXYNOS4X12_PHY_HSIC_CTRL1);
}
}
EXPORT_SYMBOL_GPL(samsung_usbphy_set_isolation_4210);

10
drivers/usb/phy/phy-samsung-usb.h
View file

@ -47,6 +47,16 @@
#define RSTCON_HLINK_SWRST (0x1 << 1)
#define RSTCON_SWRST (0x1 << 0)
/* EXYNOS4X12 */
#define EXYNOS4X12_PHY_HSIC_CTRL0 (0x04)
#define EXYNOS4X12_PHY_HSIC_CTRL1 (0x08)
#define PHYPWR_NORMAL_MASK_HSIC1 (0x7 << 12)
#define PHYPWR_NORMAL_MASK_HSIC0 (0x7 << 9)
#define PHYPWR_NORMAL_MASK_PHY1 (0x7 << 6)
#define RSTCON_HOSTPHY_SWRST (0xf << 3)
/* EXYNOS5 */
#define EXYNOS5_PHY_HOST_CTRL0 (0x00)

13
drivers/usb/phy/phy-samsung-usb2.c
View file

@ -176,8 +176,12 @@ static void samsung_usb2phy_enable(struct samsung_usbphy *sphy)
phypwr &= ~PHYPWR_NORMAL_MASK;
rstcon |= RSTCON_SWRST;
break;
case TYPE_EXYNOS4210:
case TYPE_EXYNOS4X12:
phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 |
PHYPWR_NORMAL_MASK_HSIC1 |
PHYPWR_NORMAL_MASK_PHY1);
rstcon |= RSTCON_HOSTPHY_SWRST;
case TYPE_EXYNOS4210:
phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
rstcon |= RSTCON_SWRST;
default:
@ -190,6 +194,8 @@ static void samsung_usb2phy_enable(struct samsung_usbphy *sphy)
/* reset all ports of PHY and Link */
writel(rstcon, regs + SAMSUNG_RSTCON);
udelay(10);
if (sphy->drv_data->cpu_type == TYPE_EXYNOS4X12)
rstcon &= ~RSTCON_HOSTPHY_SWRST;
rstcon &= ~RSTCON_SWRST;
writel(rstcon, regs + SAMSUNG_RSTCON);
}
@ -240,8 +246,11 @@ static void samsung_usb2phy_disable(struct samsung_usbphy *sphy)
case TYPE_S3C64XX:
phypwr |= PHYPWR_NORMAL_MASK;
break;
case TYPE_EXYNOS4210:
case TYPE_EXYNOS4X12:
phypwr |= (PHYPWR_NORMAL_MASK_HSIC0 |
PHYPWR_NORMAL_MASK_HSIC1 |
PHYPWR_NORMAL_MASK_PHY1);
case TYPE_EXYNOS4210:
phypwr |= PHYPWR_NORMAL_MASK_PHY0;
default:
break;