net/tg3: Avoid delay during MMIO access
When the EEH error is the result of a fenced host bridge, MMIO accesses can be very slow (milliseconds) to timeout and return all 1's, thus causing the driver various timeout loops to take way too long and trigger soft-lockup warnings (in addition to taking minutes to recover). It might be worthwhile to check if for any of these cases, ffffffff is a valid possible value, and if not, bail early since that means the HW is either gone or isolated. In the meantime, checking that the PCI channel is offline would be workaround of the problem. Cc: <stable@vger.kernel.org> # v3.0+ Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -744,6 +744,9 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
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status = tg3_ape_read32(tp, gnt + off);
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status = tg3_ape_read32(tp, gnt + off);
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if (status == bit)
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if (status == bit)
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break;
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break;
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if (pci_channel_offline(tp->pdev))
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break;
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udelay(10);
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udelay(10);
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}
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}
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@ -1635,6 +1638,9 @@ static void tg3_wait_for_event_ack(struct tg3 *tp)
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for (i = 0; i < delay_cnt; i++) {
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for (i = 0; i < delay_cnt; i++) {
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if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
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if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
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break;
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break;
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if (pci_channel_offline(tp->pdev))
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break;
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udelay(8);
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udelay(8);
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}
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}
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}
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}
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@ -1813,6 +1819,9 @@ static int tg3_poll_fw(struct tg3 *tp)
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for (i = 0; i < 200; i++) {
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for (i = 0; i < 200; i++) {
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if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
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if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
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return 0;
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return 0;
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if (pci_channel_offline(tp->pdev))
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return -ENODEV;
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udelay(100);
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udelay(100);
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}
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}
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return -ENODEV;
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return -ENODEV;
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@ -1823,6 +1832,15 @@ static int tg3_poll_fw(struct tg3 *tp)
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tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
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tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
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if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
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if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
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break;
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break;
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if (pci_channel_offline(tp->pdev)) {
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if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
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tg3_flag_set(tp, NO_FWARE_REPORTED);
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netdev_info(tp->dev, "No firmware running\n");
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}
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break;
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}
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udelay(10);
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udelay(10);
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}
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}
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@ -3520,6 +3538,8 @@ static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
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tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
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tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
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if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
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if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
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break;
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break;
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if (pci_channel_offline(tp->pdev))
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return -EBUSY;
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}
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}
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return (i == iters) ? -EBUSY : 0;
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return (i == iters) ? -EBUSY : 0;
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@ -8589,6 +8609,14 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, boo
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tw32_f(ofs, val);
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tw32_f(ofs, val);
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for (i = 0; i < MAX_WAIT_CNT; i++) {
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for (i = 0; i < MAX_WAIT_CNT; i++) {
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if (pci_channel_offline(tp->pdev)) {
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dev_err(&tp->pdev->dev,
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"tg3_stop_block device offline, "
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"ofs=%lx enable_bit=%x\n",
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ofs, enable_bit);
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return -ENODEV;
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}
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udelay(100);
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udelay(100);
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val = tr32(ofs);
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val = tr32(ofs);
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if ((val & enable_bit) == 0)
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if ((val & enable_bit) == 0)
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@ -8612,6 +8640,13 @@ static int tg3_abort_hw(struct tg3 *tp, bool silent)
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tg3_disable_ints(tp);
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tg3_disable_ints(tp);
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if (pci_channel_offline(tp->pdev)) {
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tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
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tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
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err = -ENODEV;
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goto err_no_dev;
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}
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tp->rx_mode &= ~RX_MODE_ENABLE;
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tp->rx_mode &= ~RX_MODE_ENABLE;
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tw32_f(MAC_RX_MODE, tp->rx_mode);
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tw32_f(MAC_RX_MODE, tp->rx_mode);
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udelay(10);
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udelay(10);
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@ -8660,6 +8695,7 @@ static int tg3_abort_hw(struct tg3 *tp, bool silent)
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err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
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err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
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err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
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err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
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err_no_dev:
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for (i = 0; i < tp->irq_cnt; i++) {
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for (i = 0; i < tp->irq_cnt; i++) {
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struct tg3_napi *tnapi = &tp->napi[i];
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struct tg3_napi *tnapi = &tp->napi[i];
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if (tnapi->hw_status)
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if (tnapi->hw_status)
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