clk: tegra: implement a reset driver
The Tegra CAR module implements both a clock and reset controller. So far, the driver exposes the clock feature via the common clock API and the reset feature using a custom API. This patch adds an implementation of the common reset framework API (include/linux/reset*.h). The legacy reset implementation will be removed once all drivers have been converted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
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@ -1460,7 +1460,8 @@ static void __init tegra114_clock_init(struct device_node *np)
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return;
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}
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clks = tegra_clk_init(TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_PERIPH_BANKS);
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clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
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TEGRA114_CLK_PERIPH_BANKS);
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if (!clks)
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return;
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@ -1398,7 +1398,7 @@ static void __init tegra124_clock_init(struct device_node *np)
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return;
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}
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clks = tegra_clk_init(TEGRA124_CLK_CLK_MAX, 6);
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clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6);
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if (!clks)
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return;
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@ -1109,7 +1109,8 @@ static void __init tegra20_clock_init(struct device_node *np)
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BUG();
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}
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clks = tegra_clk_init(TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_PERIPH_BANKS);
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clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,
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TEGRA20_CLK_PERIPH_BANKS);
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if (!clks)
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return;
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@ -1427,7 +1427,8 @@ static void __init tegra30_clock_init(struct device_node *np)
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BUG();
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}
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clks = tegra_clk_init(TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_PERIPH_BANKS);
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clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
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TEGRA30_CLK_PERIPH_BANKS);
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if (!clks)
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return;
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@ -18,6 +18,8 @@
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/clk/tegra.h>
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#include <linux/reset-controller.h>
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#include <linux/tegra-soc.h>
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#include "clk.h"
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@ -121,6 +123,35 @@ static struct tegra_clk_periph_regs periph_regs[] = {
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},
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};
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static void __iomem *clk_base;
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static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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/*
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* If peripheral is on the APB bus then we must read the APB bus to
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* flush the write operation in apb bus. This will avoid peripheral
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* access after disabling clock. Since the reset driver has no
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* knowledge of which reset IDs represent which devices, simply do
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* this all the time.
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*/
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tegra_read_chipid();
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writel_relaxed(BIT(id % 32),
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clk_base + periph_regs[id / 32].rst_set_reg);
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return 0;
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}
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static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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writel_relaxed(BIT(id % 32),
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clk_base + periph_regs[id / 32].rst_clr_reg);
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return 0;
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}
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struct tegra_clk_periph_regs *get_reg_bank(int clkid)
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{
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int reg_bank = clkid / 32;
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@ -133,8 +164,10 @@ struct tegra_clk_periph_regs *get_reg_bank(int clkid)
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}
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}
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struct clk ** __init tegra_clk_init(int num, int banks)
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struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
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{
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clk_base = regs;
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if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
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return NULL;
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@ -203,6 +236,17 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
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}
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}
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static struct reset_control_ops rst_ops = {
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.assert = tegra_clk_rst_assert,
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.deassert = tegra_clk_rst_deassert,
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};
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static struct reset_controller_dev rst_ctlr = {
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.ops = &rst_ops,
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.owner = THIS_MODULE,
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.of_reset_n_cells = 1,
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};
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void __init tegra_add_of_provider(struct device_node *np)
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{
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int i;
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@ -220,6 +264,10 @@ void __init tegra_add_of_provider(struct device_node *np)
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clk_data.clks = clks;
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clk_data.clk_num = clk_num;
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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rst_ctlr.of_node = np;
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rst_ctlr.nr_resets = clk_num * 32;
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reset_controller_register(&rst_ctlr);
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}
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void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
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@ -597,7 +597,7 @@ void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
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struct clk *clks[], int clk_max);
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struct tegra_clk_periph_regs *get_reg_bank(int clkid);
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struct clk **tegra_clk_init(int num, int periph_banks);
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struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
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struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
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