bgmac: add support for Northstar SoC (BCM4707, BCM53018)
This adds support for the Northstar SoC. This SoC does not have a PMU in bcma and no register on it should be called. In addition it support 2.5 GBit/s Ethernet to the PHY. This GMAC core is not fully working there are still problems with the DMA controller. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: David S. Miller <davem@davemloft.net>
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622a521fa4
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6df4aff972
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@ -848,6 +848,9 @@ static void bgmac_mac_speed(struct bgmac *bgmac)
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case SPEED_1000:
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set |= BGMAC_CMDCFG_ES_1000;
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break;
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case SPEED_2500:
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set |= BGMAC_CMDCFG_ES_2500;
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break;
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default:
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bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
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}
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@ -860,12 +863,26 @@ static void bgmac_mac_speed(struct bgmac *bgmac)
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static void bgmac_miiconfig(struct bgmac *bgmac)
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{
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u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
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BGMAC_DS_MM_SHIFT;
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if (imode == 0 || imode == 1) {
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bgmac->mac_speed = SPEED_100;
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struct bcma_device *core = bgmac->core;
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struct bcma_chipinfo *ci = &core->bus->chipinfo;
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u8 imode;
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if (ci->id == BCMA_CHIP_ID_BCM4707 ||
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ci->id == BCMA_CHIP_ID_BCM53018) {
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bcma_awrite32(core, BCMA_IOCTL,
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bcma_aread32(core, BCMA_IOCTL) | 0x40 |
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BGMAC_BCMA_IOCTL_SW_CLKEN);
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bgmac->mac_speed = SPEED_2500;
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bgmac->mac_duplex = DUPLEX_FULL;
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bgmac_mac_speed(bgmac);
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} else {
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imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
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BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
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if (imode == 0 || imode == 1) {
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bgmac->mac_speed = SPEED_100;
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bgmac->mac_duplex = DUPLEX_FULL;
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bgmac_mac_speed(bgmac);
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}
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}
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}
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@ -875,7 +892,7 @@ static void bgmac_chip_reset(struct bgmac *bgmac)
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struct bcma_device *core = bgmac->core;
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struct bcma_bus *bus = core->bus;
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struct bcma_chipinfo *ci = &bus->chipinfo;
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u32 flags = 0;
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u32 flags;
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u32 iost;
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int i;
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@ -903,15 +920,21 @@ static void bgmac_chip_reset(struct bgmac *bgmac)
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(ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
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iost &= ~BGMAC_BCMA_IOST_ATTACHED;
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if (iost & BGMAC_BCMA_IOST_ATTACHED) {
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flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
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if (!bgmac->has_robosw)
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flags |= BGMAC_BCMA_IOCTL_SW_RESET;
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/* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
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if (ci->id != BCMA_CHIP_ID_BCM4707) {
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flags = 0;
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if (iost & BGMAC_BCMA_IOST_ATTACHED) {
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flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
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if (!bgmac->has_robosw)
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flags |= BGMAC_BCMA_IOCTL_SW_RESET;
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}
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bcma_core_enable(core, flags);
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}
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bcma_core_enable(core, flags);
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if (core->id.rev > 2) {
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/* Request Misc PLL for corerev > 2 */
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if (core->id.rev > 2 &&
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ci->id != BCMA_CHIP_ID_BCM4707 &&
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ci->id != BCMA_CHIP_ID_BCM53018) {
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bgmac_set(bgmac, BCMA_CLKCTLST,
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BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
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bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
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@ -1049,12 +1072,16 @@ static void bgmac_enable(struct bgmac *bgmac)
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break;
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}
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rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
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rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
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bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
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mdp = (bp_clk * 128 / 1000) - 3;
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rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
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bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
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if (ci->id != BCMA_CHIP_ID_BCM4707 &&
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ci->id != BCMA_CHIP_ID_BCM53018) {
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rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
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rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
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bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
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1000000;
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mdp = (bp_clk * 128 / 1000) - 3;
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rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
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bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
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}
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}
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/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
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@ -189,6 +189,7 @@
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#define BGMAC_CMDCFG_ES_10 0x00000000
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#define BGMAC_CMDCFG_ES_100 0x00000004
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#define BGMAC_CMDCFG_ES_1000 0x00000008
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#define BGMAC_CMDCFG_ES_2500 0x0000000C
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#define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */
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#define BGMAC_CMDCFG_PAD_EN 0x00000020
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#define BGMAC_CMDCFG_CF 0x00000040
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