clk: qcom: Add support for branches/gate clocks
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -4,3 +4,4 @@ clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-regmap.o
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clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-pll.o
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clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg.o
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clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg2.o
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clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-branch.o
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159
drivers/clk/qcom/clk-branch.c
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159
drivers/clk/qcom/clk-branch.c
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@ -0,0 +1,159 @@
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/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include "clk-branch.h"
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static bool clk_branch_in_hwcg_mode(const struct clk_branch *br)
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{
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u32 val;
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if (!br->hwcg_reg)
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return 0;
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regmap_read(br->clkr.regmap, br->hwcg_reg, &val);
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return !!(val & BIT(br->hwcg_bit));
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}
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static bool clk_branch_check_halt(const struct clk_branch *br, bool enabling)
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{
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bool invert = (br->halt_check == BRANCH_HALT_ENABLE);
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u32 val;
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regmap_read(br->clkr.regmap, br->halt_reg, &val);
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val &= BIT(br->halt_bit);
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if (invert)
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val = !val;
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return !!val == !enabling;
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}
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#define BRANCH_CLK_OFF BIT(31)
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#define BRANCH_NOC_FSM_STATUS_SHIFT 28
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#define BRANCH_NOC_FSM_STATUS_MASK 0x7
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#define BRANCH_NOC_FSM_STATUS_ON (0x2 << BRANCH_NOC_FSM_STATUS_SHIFT)
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static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling)
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{
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u32 val;
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u32 mask;
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mask = BRANCH_NOC_FSM_STATUS_MASK << BRANCH_NOC_FSM_STATUS_SHIFT;
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mask |= BRANCH_CLK_OFF;
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regmap_read(br->clkr.regmap, br->halt_reg, &val);
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if (enabling) {
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val &= mask;
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return (val & BRANCH_CLK_OFF) == 0 ||
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val == BRANCH_NOC_FSM_STATUS_ON;
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} else {
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return val & BRANCH_CLK_OFF;
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}
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}
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static int clk_branch_wait(const struct clk_branch *br, bool enabling,
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bool (check_halt)(const struct clk_branch *, bool))
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{
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bool voted = br->halt_check & BRANCH_VOTED;
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const char *name = __clk_get_name(br->clkr.hw.clk);
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/* Skip checking halt bit if the clock is in hardware gated mode */
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if (clk_branch_in_hwcg_mode(br))
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return 0;
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if (br->halt_check == BRANCH_HALT_DELAY || (!enabling && voted)) {
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udelay(10);
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} else if (br->halt_check == BRANCH_HALT_ENABLE ||
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br->halt_check == BRANCH_HALT ||
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(enabling && voted)) {
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int count = 200;
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while (count-- > 0) {
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if (check_halt(br, enabling))
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return 0;
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udelay(1);
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}
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WARN(1, "%s status stuck at 'o%s'", name,
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enabling ? "ff" : "n");
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return -EBUSY;
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}
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return 0;
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}
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static int clk_branch_toggle(struct clk_hw *hw, bool en,
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bool (check_halt)(const struct clk_branch *, bool))
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{
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struct clk_branch *br = to_clk_branch(hw);
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int ret;
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if (en) {
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ret = clk_enable_regmap(hw);
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if (ret)
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return ret;
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} else {
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clk_disable_regmap(hw);
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}
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return clk_branch_wait(br, en, check_halt);
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}
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static int clk_branch_enable(struct clk_hw *hw)
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{
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return clk_branch_toggle(hw, true, clk_branch_check_halt);
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}
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static void clk_branch_disable(struct clk_hw *hw)
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{
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clk_branch_toggle(hw, false, clk_branch_check_halt);
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}
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const struct clk_ops clk_branch_ops = {
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.enable = clk_branch_enable,
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.disable = clk_branch_disable,
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.is_enabled = clk_is_enabled_regmap,
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};
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EXPORT_SYMBOL_GPL(clk_branch_ops);
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static int clk_branch2_enable(struct clk_hw *hw)
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{
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return clk_branch_toggle(hw, true, clk_branch2_check_halt);
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}
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static void clk_branch2_disable(struct clk_hw *hw)
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{
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clk_branch_toggle(hw, false, clk_branch2_check_halt);
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}
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const struct clk_ops clk_branch2_ops = {
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.enable = clk_branch2_enable,
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.disable = clk_branch2_disable,
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.is_enabled = clk_is_enabled_regmap,
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};
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EXPORT_SYMBOL_GPL(clk_branch2_ops);
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const struct clk_ops clk_branch_simple_ops = {
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.enable = clk_enable_regmap,
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.disable = clk_disable_regmap,
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.is_enabled = clk_is_enabled_regmap,
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};
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EXPORT_SYMBOL_GPL(clk_branch_simple_ops);
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56
drivers/clk/qcom/clk-branch.h
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56
drivers/clk/qcom/clk-branch.h
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@ -0,0 +1,56 @@
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/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __QCOM_CLK_BRANCH_H__
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#define __QCOM_CLK_BRANCH_H__
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#include <linux/clk-provider.h>
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#include "clk-regmap.h"
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/**
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* struct clk_branch - gating clock with status bit and dynamic hardware gating
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*
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* @hwcg_reg: dynamic hardware clock gating register
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* @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
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* @halt_reg: halt register
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* @halt_bit: ANDed with @halt_reg to test for clock halted
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* @halt_check: type of halt checking to perform
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* @clkr: handle between common and hardware-specific interfaces
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*
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* Clock which can gate its output.
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*/
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struct clk_branch {
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u32 hwcg_reg;
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u32 halt_reg;
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u8 hwcg_bit;
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u8 halt_bit;
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u8 halt_check;
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#define BRANCH_VOTED BIT(7) /* Delay on disable */
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#define BRANCH_HALT 0 /* pol: 1 = halt */
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#define BRANCH_HALT_VOTED (BRANCH_HALT | BRANCH_VOTED)
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#define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */
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#define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE | BRANCH_VOTED)
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#define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */
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struct clk_regmap clkr;
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};
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extern const struct clk_ops clk_branch_ops;
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extern const struct clk_ops clk_branch2_ops;
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extern const struct clk_ops clk_branch_simple_ops;
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#define to_clk_branch(_hw) \
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container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
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#endif
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