MIPS: Move system level config items from CPU_CAVIUM_OCTEON to CAVIUM_OCTEON_SOC
They are a property of the SoC not the CPU itself. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -732,6 +732,11 @@ config CAVIUM_OCTEON_SOC
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select ZONE_DMA32
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select ZONE_DMA32
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select HOLES_IN_ZONE
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select HOLES_IN_ZONE
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_REQUIRE_GPIOLIB
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select LIBFDT
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select USE_OF
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select ARCH_SPARSEMEM_ENABLE
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select SYS_SUPPORTS_SMP
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select NR_CPUS_DEFAULT_16
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help
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help
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This option supports all of the Octeon reference boards from Cavium
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This option supports all of the Octeon reference boards from Cavium
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Networks. It builds a kernel that dynamically determines the Octeon
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Networks. It builds a kernel that dynamically determines the Octeon
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@ -1410,16 +1415,11 @@ config CPU_SB1
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config CPU_CAVIUM_OCTEON
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config CPU_CAVIUM_OCTEON
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bool "Cavium Octeon processor"
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bool "Cavium Octeon processor"
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depends on SYS_HAS_CPU_CAVIUM_OCTEON
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depends on SYS_HAS_CPU_CAVIUM_OCTEON
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select ARCH_SPARSEMEM_ENABLE
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select CPU_HAS_PREFETCH
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select CPU_HAS_PREFETCH
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_SMP
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select NR_CPUS_DEFAULT_16
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select WEAK_ORDERING
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select WEAK_ORDERING
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_HUGEPAGES
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select CPU_SUPPORTS_HUGEPAGES
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select LIBFDT
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select USE_OF
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select USB_EHCI_BIG_ENDIAN_MMIO
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select USB_EHCI_BIG_ENDIAN_MMIO
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select MIPS_L1_CACHE_SHIFT_7
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select MIPS_L1_CACHE_SHIFT_7
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help
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help
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