powerpc: rename immap_86xx.h to fsl_guts.h, and add 85xx support
The immap_86xx.h header file only defines one data structure: the "global utilities" register set found on Freescale PowerPC SOCs. Rename this file to fsl_guts.h to reflect its true purpose, and extend it to cover the "GUTS" register set on 85xx chips. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
This commit is contained in:
Timur Tabi
Liam Girdwood
parent
f51582fd8d
commit
6e6f66226f
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@ -1,5 +1,5 @@
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/**
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* MPC86xx Internal Memory Map
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* Freecale 85xx and 86xx Global Utilties register set
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*
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* Authors: Jeff Brown
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* Timur Tabi <timur@freescale.com>
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@ -10,73 +10,112 @@
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This header file defines structures for various 86xx SOC devices that are
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* used by multiple source files.
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*/
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#ifndef __ASM_POWERPC_IMMAP_86XX_H__
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#define __ASM_POWERPC_IMMAP_86XX_H__
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#ifndef __ASM_POWERPC_FSL_GUTS_H__
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#define __ASM_POWERPC_FSL_GUTS_H__
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#ifdef __KERNEL__
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/* Global Utility Registers */
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struct ccsr_guts {
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/*
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* These #ifdefs are safe because it's not possible to build a kernel that
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* runs on e500 and e600 cores.
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*/
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#if !defined(CONFIG_PPC_85xx) && !defined(CONFIG_PPC_86xx)
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#error Only 85xx and 86xx SOCs are supported
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#endif
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/**
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* Global Utility Registers.
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*
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* Not all registers defined in this structure are available on all chips, so
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* you are expected to know whether a given register actually exists on your
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* chip before you access it.
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*
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* Also, some registers are similar on different chips but have slightly
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* different names. In these cases, one name is chosen to avoid extraneous
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* #ifdefs.
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*/
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#ifdef CONFIG_PPC_85xx
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struct ccsr_guts_85xx {
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#else
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struct ccsr_guts_86xx {
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#endif
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__be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
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__be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
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__be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
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__be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
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__be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
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u8 res1[0x20 - 0x14];
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__be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
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u8 res018[0x20 - 0x18];
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__be32 porcir; /* 0x.0020 - POR Configuration Information Register */
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u8 res2[0x30 - 0x24];
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u8 res024[0x30 - 0x24];
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__be32 gpiocr; /* 0x.0030 - GPIO Control Register */
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u8 res3[0x40 - 0x34];
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u8 res034[0x40 - 0x34];
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__be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
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u8 res4[0x50 - 0x44];
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u8 res044[0x50 - 0x44];
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__be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
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u8 res5[0x60 - 0x54];
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u8 res054[0x60 - 0x54];
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__be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
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u8 res6[0x70 - 0x64];
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__be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
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__be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
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u8 res06c[0x70 - 0x6c];
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__be32 devdisr; /* 0x.0070 - Device Disable Control */
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__be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
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u8 res7[0x80 - 0x78];
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u8 res078[0x7c - 0x78];
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__be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
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__be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
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u8 res8[0x90 - 0x84];
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__be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
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__be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
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__be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
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__be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
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__be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
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u8 res9[0xA0 - 0x98];
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__be32 ectrstcr; /* 0x.0098 - Exception reset control register */
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__be32 autorstsr; /* 0x.009c - Automatic reset status register */
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__be32 pvr; /* 0x.00a0 - Processor Version Register */
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__be32 svr; /* 0x.00a4 - System Version Register */
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u8 res10[0xB0 - 0xA8];
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u8 res0a8[0xb0 - 0xa8];
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__be32 rstcr; /* 0x.00b0 - Reset Control Register */
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u8 res11[0xC0 - 0xB4];
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u8 res0b4[0xc0 - 0xb4];
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#ifdef CONFIG_PPC_85xx
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__be32 iovselsr; /* 0x.00c0 - I/O voltage select status register */
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#else
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__be32 elbcvselcr; /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */
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u8 res12[0x800 - 0xC4];
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#endif
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u8 res0c4[0x224 - 0xc4];
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__be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
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__be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
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u8 res22c[0x800 - 0x22c];
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__be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
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u8 res13[0x900 - 0x804];
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u8 res804[0x900 - 0x804];
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__be32 ircr; /* 0x.0900 - Infrared Control Register */
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u8 res14[0x908 - 0x904];
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u8 res904[0x908 - 0x904];
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__be32 dmacr; /* 0x.0908 - DMA Control Register */
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u8 res15[0x914 - 0x90C];
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u8 res90c[0x914 - 0x90c];
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__be32 elbccr; /* 0x.0914 - eLBC Control Register */
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u8 res16[0xB20 - 0x918];
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u8 res918[0xb20 - 0x918];
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__be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
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__be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
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__be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
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u8 res17[0xE00 - 0xB2C];
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u8 resb2c[0xe00 - 0xb2c];
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__be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
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u8 res18[0xE10 - 0xE04];
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u8 rese04[0xe10 - 0xe04];
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__be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
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u8 res19[0xE20 - 0xE14];
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u8 rese14[0xe20 - 0xe14];
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__be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
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u8 res20[0xF04 - 0xE24];
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__be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
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u8 rese28[0xf04 - 0xe28];
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__be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
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__be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
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u8 res21[0xF40 - 0xF0C];
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__be32 srds2cr0; /* 0x.0f40 - SerDes1 Control Register 0 */
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__be32 srds2cr1; /* 0x.0f44 - SerDes1 Control Register 0 */
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u8 resf0c[0xf2c - 0xf0c];
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__be32 itcr; /* 0x.0f2c - Internal transaction control register */
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u8 resf30[0xf40 - 0xf30];
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__be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
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__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
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} __attribute__ ((packed));
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#ifdef CONFIG_PPC_86xx
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#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
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#define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */
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@ -93,7 +132,7 @@ struct ccsr_guts {
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* ch: The channel on the DMA controller (0, 1, 2, or 3)
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* device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
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*/
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static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
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static inline void guts_set_dmacr(struct ccsr_guts_86xx __iomem *guts,
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unsigned int co, unsigned int ch, unsigned int device)
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{
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unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
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@ -129,7 +168,7 @@ static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
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* ch: The channel on the DMA controller (0, 1, 2, or 3)
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* value: the new value for the bit (0 or 1)
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*/
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static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
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static inline void guts_set_pmuxcr_dma(struct ccsr_guts_86xx __iomem *guts,
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unsigned int co, unsigned int ch, unsigned int value)
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{
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if ((ch == 0) || (ch == 3)) {
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@ -152,5 +191,7 @@ static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
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#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
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#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
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#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
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#endif /* __KERNEL__ */
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#endif
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#endif
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#endif
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@ -24,8 +24,6 @@
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <asm/immap_86xx.h>
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#include "fsl_ssi.h"
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/**
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@ -14,7 +14,7 @@
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#include <linux/interrupt.h>
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#include <linux/of_device.h>
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#include <sound/soc.h>
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#include <asm/immap_86xx.h>
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#include <asm/fsl_guts.h>
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#include "fsl_dma.h"
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#include "fsl_ssi.h"
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@ -57,9 +57,9 @@ static int mpc8610_hpcd_machine_probe(struct platform_device *sound_device)
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struct snd_soc_card *card = platform_get_drvdata(sound_device);
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struct mpc8610_hpcd_data *machine_data =
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container_of(card, struct mpc8610_hpcd_data, card);
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struct ccsr_guts __iomem *guts;
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struct ccsr_guts_86xx __iomem *guts;
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guts = ioremap(guts_phys, sizeof(struct ccsr_guts));
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guts = ioremap(guts_phys, sizeof(struct ccsr_guts_86xx));
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if (!guts) {
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dev_err(card->dev, "could not map global utilities\n");
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return -ENOMEM;
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@ -142,9 +142,9 @@ static int mpc8610_hpcd_machine_remove(struct platform_device *sound_device)
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struct snd_soc_card *card = platform_get_drvdata(sound_device);
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struct mpc8610_hpcd_data *machine_data =
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container_of(card, struct mpc8610_hpcd_data, card);
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struct ccsr_guts __iomem *guts;
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struct ccsr_guts_86xx __iomem *guts;
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guts = ioremap(guts_phys, sizeof(struct ccsr_guts));
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guts = ioremap(guts_phys, sizeof(struct ccsr_guts_86xx));
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if (!guts) {
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dev_err(card->dev, "could not map global utilities\n");
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return -ENOMEM;
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