e1000e: enable ECC correction on 82571 silicon
This change enables ECC correction for the packet buffer on all 82571 silicon. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -973,6 +973,12 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
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ew32(CTRL_EXT, reg);
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}
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if (hw->mac.type == e1000_82571) {
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reg = er32(PBA_ECC);
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reg |= E1000_PBA_ECC_CORR_EN;
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ew32(PBA_ECC, reg);
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}
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/* PCI-Ex Control Register */
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if (hw->mac.type == e1000_82574) {
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reg = er32(GCR);
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@ -372,6 +372,13 @@
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#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
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#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
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/* PBA ECC Register */
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#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
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#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
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#define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */
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#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
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#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */
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/*
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* This defines the bits that are set in the Interrupt Mask
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* Set/Read Register. Each bit is documented below:
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@ -87,6 +87,7 @@ enum e1e_registers {
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E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
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E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
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E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
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E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
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E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
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E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
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E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
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