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clk: tegra: add ac97 controller clock 

AC97 controller clock is hardwired to pll_a_out0.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
wifi-calibration
Lucas Stach 2013-05-06 15:11:11 -06:00 committed by Olof Johansson
parent 7e94984495
commit 6ec3240047
1 changed files with 8 additions and 0 deletions
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8
drivers/clk/tegra/clk-tegra20.c
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@ -872,6 +872,14 @@ static void __init tegra20_periph_clk_init(void)
struct clk *clk;
int i;
/* ac97 */
clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
TEGRA_PERIPH_ON_APB,
clk_base, 0, 3, &periph_l_regs,
periph_clk_enb_refcnt);
clk_register_clkdev(clk, NULL, "tegra20-ac97");
clks[ac97] = clk;
/* apbdma */
clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
0, 34, &periph_h_regs,