iio: stm32 trigger: Add support for TRGO2 triggers
Add support for TRGO2 trigger that can be found on STM32F7. Add additional master modes supported by TRGO2. Register additional "tim[1/8]_trgo2" triggers for timer1 & timer8. Detect TRGO2 timer capability (master mode selection 2). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Acked-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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@ -16,6 +16,54 @@ Description:
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- "OC2REF" : OC2REF signal is used as trigger output.
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- "OC3REF" : OC3REF signal is used as trigger output.
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- "OC4REF" : OC4REF signal is used as trigger output.
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Additional modes (on TRGO2 only):
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- "OC5REF" : OC5REF signal is used as trigger output.
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- "OC6REF" : OC6REF signal is used as trigger output.
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- "compare_pulse_OC4REF":
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OC4REF rising or falling edges generate pulses.
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- "compare_pulse_OC6REF":
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OC6REF rising or falling edges generate pulses.
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- "compare_pulse_OC4REF_r_or_OC6REF_r":
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OC4REF or OC6REF rising edges generate pulses.
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- "compare_pulse_OC4REF_r_or_OC6REF_f":
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OC4REF rising or OC6REF falling edges generate pulses.
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- "compare_pulse_OC5REF_r_or_OC6REF_r":
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OC5REF or OC6REF rising edges generate pulses.
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- "compare_pulse_OC5REF_r_or_OC6REF_f":
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OC5REF rising or OC6REF falling edges generate pulses.
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+-----------+ +-------------+ +---------+
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| Prescaler +-> | Counter | +-> | Master | TRGO(2)
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+-----------+ +--+--------+-+ |-> | Control +-->
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| | || +---------+
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+--v--------+-+ OCxREF || +---------+
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| Chx compare +----------> | Output | ChX
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+-----------+-+ | | Control +-->
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. | | +---------+
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. | | .
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+-----------v-+ OC6REF | .
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| Ch6 compare +---------+>
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+-------------+
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Example with: "compare_pulse_OC4REF_r_or_OC6REF_r":
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X
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X X
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X . . X
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X . . X
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X . . X
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count X . . . . X
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. . . .
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. . . .
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+---------------+
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OC4REF | . . |
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+-+ . . +-+
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. +---+ .
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OC6REF . | | .
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+-------+ +-------+
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+-+ +-+
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TRGO2 | | | |
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+-+ +---+ +---------+
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What: /sys/bus/iio/devices/triggerX/master_mode
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KernelVersion: 4.11
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@ -14,19 +14,19 @@
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#define MAX_TRIGGERS 6
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#define MAX_TRIGGERS 7
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#define MAX_VALIDS 5
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/* List the triggers created by each timer */
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static const void *triggers_table[][MAX_TRIGGERS] = {
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{ TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
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{ TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
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{ TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
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{ TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
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{ TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
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{ TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
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{ TIM6_TRGO,},
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{ TIM7_TRGO,},
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{ TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
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{ TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
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{ TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
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{ }, /* timer 10 */
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{ }, /* timer 11 */
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@ -56,9 +56,16 @@ struct stm32_timer_trigger {
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u32 max_arr;
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const void *triggers;
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const void *valids;
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bool has_trgo2;
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};
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static bool stm32_timer_is_trgo2_name(const char *name)
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{
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return !!strstr(name, "trgo2");
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}
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static int stm32_timer_start(struct stm32_timer_trigger *priv,
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struct iio_trigger *trig,
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unsigned int frequency)
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{
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unsigned long long prd, div;
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@ -102,7 +109,12 @@ static int stm32_timer_start(struct stm32_timer_trigger *priv,
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
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/* Force master mode to update mode */
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regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0x20);
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if (stm32_timer_is_trgo2_name(trig->name))
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regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
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0x2 << TIM_CR2_MMS2_SHIFT);
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else
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regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
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0x2 << TIM_CR2_MMS_SHIFT);
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/* Make sure that registers are updated */
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regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
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@ -150,7 +162,7 @@ static ssize_t stm32_tt_store_frequency(struct device *dev,
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if (freq == 0) {
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stm32_timer_stop(priv);
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} else {
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ret = stm32_timer_start(priv, freq);
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ret = stm32_timer_start(priv, trig, freq);
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if (ret)
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return ret;
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}
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@ -183,6 +195,9 @@ static IIO_DEV_ATTR_SAMP_FREQ(0660,
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stm32_tt_read_frequency,
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stm32_tt_store_frequency);
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#define MASTER_MODE_MAX 7
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#define MASTER_MODE2_MAX 15
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static char *master_mode_table[] = {
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"reset",
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"enable",
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@ -191,7 +206,16 @@ static char *master_mode_table[] = {
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"OC1REF",
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"OC2REF",
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"OC3REF",
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"OC4REF"
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"OC4REF",
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/* Master mode selection 2 only */
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"OC5REF",
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"OC6REF",
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"compare_pulse_OC4REF",
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"compare_pulse_OC6REF",
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"compare_pulse_OC4REF_r_or_OC6REF_r",
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"compare_pulse_OC4REF_r_or_OC6REF_f",
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"compare_pulse_OC5REF_r_or_OC6REF_r",
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"compare_pulse_OC5REF_r_or_OC6REF_f",
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};
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static ssize_t stm32_tt_show_master_mode(struct device *dev,
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@ -199,10 +223,15 @@ static ssize_t stm32_tt_show_master_mode(struct device *dev,
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char *buf)
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{
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struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
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struct iio_trigger *trig = to_iio_trigger(dev);
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u32 cr2;
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regmap_read(priv->regmap, TIM_CR2, &cr2);
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cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
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if (stm32_timer_is_trgo2_name(trig->name))
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cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
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else
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cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
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return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
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}
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@ -212,13 +241,25 @@ static ssize_t stm32_tt_store_master_mode(struct device *dev,
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const char *buf, size_t len)
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{
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struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
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struct iio_trigger *trig = to_iio_trigger(dev);
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u32 mask, shift, master_mode_max;
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int i;
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for (i = 0; i < ARRAY_SIZE(master_mode_table); i++) {
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if (stm32_timer_is_trgo2_name(trig->name)) {
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mask = TIM_CR2_MMS2;
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shift = TIM_CR2_MMS2_SHIFT;
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master_mode_max = MASTER_MODE2_MAX;
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} else {
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mask = TIM_CR2_MMS;
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shift = TIM_CR2_MMS_SHIFT;
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master_mode_max = MASTER_MODE_MAX;
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}
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for (i = 0; i <= master_mode_max; i++) {
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if (!strncmp(master_mode_table[i], buf,
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strlen(master_mode_table[i]))) {
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regmap_update_bits(priv->regmap, TIM_CR2,
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TIM_CR2_MMS, i << TIM_CR2_MMS_SHIFT);
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regmap_update_bits(priv->regmap, TIM_CR2, mask,
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i << shift);
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/* Make sure that registers are updated */
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regmap_update_bits(priv->regmap, TIM_EGR,
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TIM_EGR_UG, TIM_EGR_UG);
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@ -229,8 +270,31 @@ static ssize_t stm32_tt_store_master_mode(struct device *dev,
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return -EINVAL;
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}
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static IIO_CONST_ATTR(master_mode_available,
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"reset enable update compare_pulse OC1REF OC2REF OC3REF OC4REF");
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static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_trigger *trig = to_iio_trigger(dev);
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unsigned int i, master_mode_max;
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size_t len = 0;
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if (stm32_timer_is_trgo2_name(trig->name))
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master_mode_max = MASTER_MODE2_MAX;
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else
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master_mode_max = MASTER_MODE_MAX;
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for (i = 0; i <= master_mode_max; i++)
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len += scnprintf(buf + len, PAGE_SIZE - len,
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"%s ", master_mode_table[i]);
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/* replace trailing space by newline */
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buf[len - 1] = '\n';
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return len;
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}
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static IIO_DEVICE_ATTR(master_mode_available, 0444,
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stm32_tt_show_master_mode_avail, NULL, 0);
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static IIO_DEVICE_ATTR(master_mode, 0660,
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stm32_tt_show_master_mode,
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@ -240,7 +304,7 @@ static IIO_DEVICE_ATTR(master_mode, 0660,
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static struct attribute *stm32_trigger_attrs[] = {
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&iio_dev_attr_sampling_frequency.dev_attr.attr,
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&iio_dev_attr_master_mode.dev_attr.attr,
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&iio_const_attr_master_mode_available.dev_attr.attr,
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&iio_dev_attr_master_mode_available.dev_attr.attr,
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NULL,
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};
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@ -264,6 +328,12 @@ static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
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while (cur && *cur) {
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struct iio_trigger *trig;
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bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
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if (cur_is_trgo2 && !priv->has_trgo2) {
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cur++;
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continue;
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}
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trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
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if (!trig)
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@ -277,7 +347,7 @@ static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
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* should only be available on trgo trigger which
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* is always the first in the list.
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*/
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if (cur == priv->triggers)
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if (cur == priv->triggers || cur_is_trgo2)
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trig->dev.groups = stm32_trigger_attr_groups;
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iio_trigger_set_drvdata(trig, priv);
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@ -584,6 +654,20 @@ bool is_stm32_timer_trigger(struct iio_trigger *trig)
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}
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EXPORT_SYMBOL(is_stm32_timer_trigger);
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static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
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{
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u32 val;
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/*
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* Master mode selection 2 bits can only be written and read back when
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* timer supports it.
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*/
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regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
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regmap_read(priv->regmap, TIM_CR2, &val);
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regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
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priv->has_trgo2 = !!val;
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}
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static int stm32_timer_trigger_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -614,6 +698,7 @@ static int stm32_timer_trigger_probe(struct platform_device *pdev)
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priv->max_arr = ddata->max_arr;
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priv->triggers = triggers_table[index];
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priv->valids = valids_table[index];
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stm32_timer_detect_trgo2(priv);
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ret = stm32_setup_iio_triggers(priv);
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if (ret)
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@ -10,6 +10,7 @@
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#define _STM32_TIMER_TRIGGER_H_
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#define TIM1_TRGO "tim1_trgo"
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#define TIM1_TRGO2 "tim1_trgo2"
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#define TIM1_CH1 "tim1_ch1"
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#define TIM1_CH2 "tim1_ch2"
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#define TIM1_CH3 "tim1_ch3"
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#define TIM7_TRGO "tim7_trgo"
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#define TIM8_TRGO "tim8_trgo"
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#define TIM8_TRGO2 "tim8_trgo2"
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#define TIM8_CH1 "tim8_ch1"
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#define TIM8_CH2 "tim8_ch2"
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#define TIM8_CH3 "tim8_ch3"
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@ -34,6 +34,7 @@
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#define TIM_CR1_DIR BIT(4) /* Counter Direction */
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#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
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#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
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#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */
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#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
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#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
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#define TIM_DIER_UIE BIT(0) /* Update interrupt */
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@ -60,6 +61,7 @@
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#define MAX_TIM_PSC 0xFFFF
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#define TIM_CR2_MMS_SHIFT 4
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#define TIM_CR2_MMS2_SHIFT 20
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#define TIM_SMCR_TS_SHIFT 4
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#define TIM_BDTR_BKF_MASK 0xF
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#define TIM_BDTR_BKF_SHIFT 16
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