nios2 fixes for v4.0-final
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.5 (GNU/Linux) iQIVAwUAVSdBClWoEK+e3syCAQLs1g//aIlUOzsi3plc+Q9s9TdQX5Gw46rmJ27/ pP4A1rwgW2NassU/97MUfVr+XiaOpdzEP8tXIoeR1qLUV1e+XT3f1OqczTgdIpcY 7rSN5UNE9zf20U9eMnexBeLmU+db/JvQx0UryMsS+pRDGQLJUiVCkDkQJ/EGtY0F 7WEE7rZKJwwdw9deiSaxoXyHEsL0jtDTlvZ1GBlCFBm5d3NCzTReI82muhih9R/y 4OBnfeS4l87o4IgY2Fjcduh9pqwUnwu479sMBZm3ZfGiIJINvi/XzTaZsoLS7AiQ aYfMBK1Yn7JMrFW8j+2gMf1GN26P2v9+cZ+sWf/BfnAnXGGqerFRv/A+BMU0HVzI KAbHLGA4bRuYxPIwz+nY5Amr4a7W4ySVXBooX6egVPSLhClJYZubDPoTUhBs9mTc PwBTBa0NAL4BkKHJOSDh2KJO56HhJ+XoxN4OpdjgLom6U8Jqa9BRNT6dadBxDcye Qhcs1GuTaDYxRlx5TMKFnTuE1nMPxjxfgV0JfXWlf0M0fum+nQv5rJXfO+6m6g25 ge+cGyJ4QAmGhzLtUuO3AgYqc4U0w3T7dTFKDrVg5BPGaiS/cGiqnu5yfOkLDn85 jeFyQbyeOtXQhkMK0ThoPKNPv+TMtBvLWdN6YPSTPdX9LKiNCY+AIuKdt1PrVMum T8fJ2yzNbnU= =uL58 -----END PGP SIGNATURE----- Merge tag 'nios2-fixes-v4.0-final' of git://git.rocketboards.org/linux-socfpga-next Pull arch/nios2 fixes from Ley Foon Tan: "There are 3 arch/nios2 fixes for 4.0 final: - fix cache coherency issue when debugging with gdb - move restart_block to struct task_struct (aligned with other architectures) - fix for missing registers defines for ptrace" * tag 'nios2-fixes-v4.0-final' of git://git.rocketboards.org/linux-socfpga-next: nios2: fix cache coherency issue when debug with gdb nios2: add missing ptrace registers defines nios2: signal: Move restart_block to struct task_struct
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commit
6fb805fb10
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@ -47,7 +47,6 @@ struct thread_info {
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0-0x7FFFFFFF for user-thead
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0-0xFFFFFFFF for kernel-thread
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*/
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struct restart_block restart_block;
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struct pt_regs *regs;
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};
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@ -64,9 +63,6 @@ struct thread_info {
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.cpu = 0, \
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.preempt_count = INIT_PREEMPT_COUNT, \
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.addr_limit = KERNEL_DS, \
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.restart_block = { \
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.fn = do_no_restart_syscall, \
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}, \
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}
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#define init_thread_info (init_thread_union.thread_info)
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@ -60,12 +60,17 @@
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#define PTR_IPENDING 37
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#define PTR_CPUID 38
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#define PTR_CTL6 39
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#define PTR_CTL7 40
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#define PTR_EXCEPTION 40
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#define PTR_PTEADDR 41
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#define PTR_TLBACC 42
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#define PTR_TLBMISC 43
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#define PTR_ECCINJ 44
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#define PTR_BADADDR 45
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#define PTR_CONFIG 46
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#define PTR_MPUBASE 47
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#define PTR_MPUACC 48
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#define NUM_PTRACE_REG (PTR_TLBMISC + 1)
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#define NUM_PTRACE_REG (PTR_MPUACC + 1)
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/* User structures for general purpose registers. */
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struct user_pt_regs {
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@ -161,7 +161,7 @@ ENTRY(inthandler)
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***********************************************************************
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*/
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ENTRY(handle_trap)
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ldw r24, -4(ea) /* instruction that caused the exception */
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ldwio r24, -4(ea) /* instruction that caused the exception */
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srli r24, r24, 4
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andi r24, r24, 0x7c
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movia r9,trap_table
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@ -43,7 +43,7 @@ static inline int rt_restore_ucontext(struct pt_regs *regs,
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int err;
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/* Always make any pending restarted system calls return -EINTR */
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current_thread_info()->restart_block.fn = do_no_restart_syscall;
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current->restart_block.fn = do_no_restart_syscall;
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err = __get_user(temp, &uc->uc_mcontext.version);
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if (temp != MCONTEXT_VERSION)
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@ -23,9 +23,6 @@ static void __flush_dcache(unsigned long start, unsigned long end)
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end += (cpuinfo.dcache_line_size - 1);
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end &= ~(cpuinfo.dcache_line_size - 1);
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if (end > start + cpuinfo.dcache_size)
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end = start + cpuinfo.dcache_size;
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for (addr = start; addr < end; addr += cpuinfo.dcache_line_size) {
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__asm__ __volatile__ (" flushda 0(%0)\n"
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: /* Outputs */
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