i2c: octeon: thunderx: Limit register access retries
Do not infinitely retry register readq and writeq operations in order to not lock up the CPU in case the TWSI gets stuck. Return -ETIMEDOUT in case of a failed data read. For all other cases just return so subsequent operations will fail. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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@ -381,7 +381,9 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
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if (result)
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return result;
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data[i] = octeon_i2c_data_read(i2c);
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data[i] = octeon_i2c_data_read(i2c, &result);
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if (result)
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return result;
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if (recv_len && i == 0) {
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if (data[i] > I2C_SMBUS_BLOCK_MAX + 1)
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return -EPROTO;
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@ -5,6 +5,7 @@
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#include <linux/i2c.h>
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#include <linux/i2c-smbus.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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@ -144,9 +145,9 @@ static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8
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u64 tmp;
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__raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI(i2c));
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do {
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tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
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} while ((tmp & SW_TWSI_V) != 0);
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readq_poll_timeout(i2c->twsi_base + SW_TWSI(i2c), tmp, tmp & SW_TWSI_V,
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I2C_OCTEON_EVENT_WAIT, i2c->adap.timeout);
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}
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#define octeon_i2c_ctl_write(i2c, val) \
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@ -163,24 +164,28 @@ static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8
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*
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* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
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*/
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static inline u8 octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg)
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static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg,
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int *error)
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{
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u64 tmp;
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int ret;
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__raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI(i2c));
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do {
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tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
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} while ((tmp & SW_TWSI_V) != 0);
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ret = readq_poll_timeout(i2c->twsi_base + SW_TWSI(i2c), tmp,
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tmp & SW_TWSI_V, I2C_OCTEON_EVENT_WAIT,
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i2c->adap.timeout);
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if (error)
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*error = ret;
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return tmp & 0xFF;
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}
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#define octeon_i2c_ctl_read(i2c) \
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octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL)
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#define octeon_i2c_data_read(i2c) \
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octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA)
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octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL, NULL)
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#define octeon_i2c_data_read(i2c, error) \
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octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA, error)
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#define octeon_i2c_stat_read(i2c) \
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octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT)
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octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL)
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/**
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* octeon_i2c_read_int - read the TWSI_INT register
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