drm/nouveau/gr/gf100-: split out per-gpc address calculation macro
There's a few places where we need to access a GPC register from ucode, but outside of the falcon's io address space. To do this we need to calculate the offset based on which GPC we're executing on. This used to be done manually, but we've since found a "base" offset that can be added by the hardware. To use this, an extra bit needs to be set in the register address, which is what this macro achieves. There should be no functional change from this commit. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -52,10 +52,12 @@ mmio_list_base:
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#endif
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#ifdef INCLUDE_CODE
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#define gpc_addr(reg,addr) /*
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*/ imm32(reg,addr) /*
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*/ or reg NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE
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#define gpc_wr32(addr,reg) /*
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*/ gpc_addr($r14,addr) /*
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*/ mov b32 $r15 reg /*
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*/ imm32($r14, addr) /*
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*/ or $r14 NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE /*
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*/ call(nv_wr32)
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// reports an exception to the host
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@ -356,33 +356,33 @@ uint32_t gm107_grgpc_code[] = {
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0x02687e2f,
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0x002fbb00,
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0x0f003fbb,
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0x8effb23f,
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0xf0501d60,
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0x8f7e01e5,
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0x0c0f0000,
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0xa88effb2,
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0xe5f0501d,
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0x008f7e01,
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0x03147e00,
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0xb23f0f00,
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0x1d608eff,
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0x1d608e3f,
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0x01e5f050,
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0x8f7effb2,
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0x0c0f0000,
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0x501da88e,
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0xb201e5f0,
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0x008f7eff,
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0x03147e00,
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0x8e3f0f00,
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0xf0501d60,
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0xffb201e5,
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0x00008f7e,
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0xffb2000f,
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0x501d9c8e,
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0x7e01e5f0,
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0x9c8e000f,
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0xe5f0501d,
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0x7effb201,
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0x0f00008f,
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0x03147e01,
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0x8effb200,
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0xf0501da8,
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0x8f7e01e5,
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0xff0f0000,
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0x988effb2,
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0xe5f0501d,
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0x008f7e01,
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0xb2020f00,
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0x1da88eff,
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0x1da88e00,
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0x01e5f050,
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0x8f7effb2,
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0xff0f0000,
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0x501d988e,
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0xb201e5f0,
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0x008f7eff,
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0x8e020f00,
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0xf0501da8,
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0xffb201e5,
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0x00008f7e,
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0x0003147e,
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0x85050498,
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@ -414,13 +414,13 @@ uint32_t gm107_grgpc_code[] = {
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0x0050b7bf,
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0x0142b608,
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0x0fa81bf4,
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0x8effb23f,
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0xf0501d60,
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0x8f7e01e5,
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0x1d608e3f,
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0x01e5f050,
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0x8f7effb2,
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0x0d0f0000,
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0xa88effb2,
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0xe5f0501d,
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0x008f7e01,
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0x501da88e,
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0xb201e5f0,
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0x008f7eff,
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0x03147e00,
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0x01008000,
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0x0003f602,
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@ -491,9 +491,9 @@ uint32_t gm107_grgpc_code[] = {
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0x8000f804,
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0xf6028100,
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0x04bd000f,
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0xc48effb2,
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0xe5f0501d,
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0x008f7e01,
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0x501dc48e,
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0xb201e5f0,
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0x008f7eff,
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0x0711f400,
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0x0006217e,
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/* 0x0664: ctx_xfer_not_load */
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@ -505,23 +505,23 @@ uint32_t gm107_grgpc_code[] = {
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0x4afc8003,
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0x0002f602,
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0x0c0f04bd,
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0xa88effb2,
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0xe5f0501d,
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0x008f7e01,
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0x501da88e,
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0xb201e5f0,
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0x008f7eff,
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0x03147e00,
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0xb23f0f00,
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0x1d608eff,
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0x01e5f050,
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0x8e3f0f00,
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0xf0501d60,
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0xffb201e5,
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0x00008f7e,
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0xffb2000f,
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0x501d9c8e,
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0x7e01e5f0,
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0x9c8e000f,
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0xe5f0501d,
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0x7effb201,
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0x0f00008f,
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0x03147e01,
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0x01fcf000,
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0xb203f0b6,
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0x1da88eff,
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0x01e5f050,
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0x8e03f0b6,
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0xf0501da8,
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0xffb201e5,
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0x00008f7e,
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0xf001acf0,
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0x008b02a5,
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@ -553,9 +553,9 @@ uint32_t gm107_grgpc_code[] = {
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0x1a12f406,
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/* 0x073c: ctx_xfer_post */
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0x0002277e,
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0xffb20d0f,
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0x501da88e,
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0x7e01e5f0,
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0xa88e0d0f,
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0xe5f0501d,
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0x7effb201,
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0x7e00008f,
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/* 0x0753: ctx_xfer_done */
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0x7e000314,
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