[SPARC64]: Add prefetch support.
The implementation is optimal for UltraSPARC-III and later. It will work, however suboptimally, on UltraSPARC-II and be treated as a NOP on UltraSPARC-I. It is not worth code patching this thing as the highest cost is the code space, and code patching cannot eliminate that. Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -192,6 +192,40 @@ extern unsigned long get_wchan(struct task_struct *task);
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#define cpu_relax() barrier()
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/* Prefetch support. This is tuned for UltraSPARC-III and later.
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* UltraSPARC-I will treat these as nops, and UltraSPARC-II has
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* a shallower prefetch queue than later chips.
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*/
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#define ARCH_HAS_PREFETCH
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#define ARCH_HAS_PREFETCHW
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#define ARCH_HAS_SPINLOCK_PREFETCH
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static inline void prefetch(const void *x)
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{
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/* We do not use the read prefetch mnemonic because that
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* prefetches into the prefetch-cache which only is accessible
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* by floating point operations in UltraSPARC-III and later.
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* By contrast, "#one_write" prefetches into the L2 cache
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* in shared state.
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*/
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__asm__ __volatile__("prefetch [%0], #one_write"
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: /* no outputs */
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: "r" (x));
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}
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static inline void prefetchw(const void *x)
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{
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/* The most optimal prefetch to use for writes is
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* "#n_writes". This brings the cacheline into the
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* L2 cache in "owned" state.
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*/
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__asm__ __volatile__("prefetch [%0], #n_writes"
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: /* no outputs */
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: "r" (x));
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}
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#define spin_lock_prefetch(x) prefetchw(x)
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#endif /* !(__ASSEMBLY__) */
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#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
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