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MLK-15932-7 gpu: imx: dpu: common: Add scalers support in dpu plane group 

This patch adds scalers support in dpu plane group.  A module parameter,
i.e., display_plane_video_proc, is introduced to enable or disable video
processing capability of display plane, since some video processing units
are shared with capture controllers.  By default, it is enabled.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
pull/10/head
Liu Ying 2017-07-10 12:47:10 +08:00 committed by Jason Liu
parent 71d758e071
commit 70a29aaaab
2 changed files with 38 additions and 0 deletions
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32
drivers/gpu/imx/dpu/dpu-common.c
View File

@ -28,6 +28,11 @@
#include <video/dpu.h>
#include "dpu-prv.h"
static bool display_plane_video_proc = true;
module_param(display_plane_video_proc, bool, 0444);
MODULE_PARM_DESC(display_plane_video_proc,
"Enable video processing for display [default=true]");
#define DPU_CM_REG_DEFINE1(name1, name2) \
static inline u32 name1(const struct cm_reg_ofs *ofs) \
{ \
@ -761,11 +766,29 @@ static int dpu_get_plane_resource(struct dpu_soc *dpu,
if (IS_ERR(res->fd[i]))
return PTR_ERR(res->fd[i]);
}
/* HScaler could be shared with capture. */
if (display_plane_video_proc) {
for (i = 0; i < ARRAY_SIZE(res->hs); i++) {
res->hs[i] = dpu_hs_get(dpu, hs_ids[i]);
if (IS_ERR(res->hs[i]))
return PTR_ERR(res->hs[i]);
}
grp->hw_plane_hscaler_num = ARRAY_SIZE(res->hs);
}
for (i = 0; i < lbs->num; i++) {
res->lb[i] = dpu_lb_get(dpu, i);
if (IS_ERR(res->lb[i]))
return PTR_ERR(res->lb[i]);
}
/* VScaler could be shared with capture. */
if (display_plane_video_proc) {
for (i = 0; i < ARRAY_SIZE(res->vs); i++) {
res->vs[i] = dpu_vs_get(dpu, vs_ids[i]);
if (IS_ERR(res->vs[i]))
return PTR_ERR(res->vs[i]);
}
grp->hw_plane_vscaler_num = ARRAY_SIZE(res->vs);
}
grp->hw_plane_num = fds->num;
@ -789,10 +812,18 @@ static void dpu_put_plane_resource(struct dpu_plane_res *res)
if (!IS_ERR_OR_NULL(res->fd[i]))
dpu_fd_put(res->fd[i]);
}
for (i = 0; i < ARRAY_SIZE(res->hs); i++) {
if (!IS_ERR_OR_NULL(res->hs[i]))
dpu_hs_put(res->hs[i]);
}
for (i = 0; i < ARRAY_SIZE(res->lb); i++) {
if (!IS_ERR_OR_NULL(res->lb[i]))
dpu_lb_put(res->lb[i]);
}
for (i = 0; i < ARRAY_SIZE(res->vs); i++) {
if (!IS_ERR_OR_NULL(res->vs[i]))
dpu_vs_put(res->vs[i]);
}
grp->hw_plane_num = 0;
}
@ -832,6 +863,7 @@ static int dpu_add_client_devices(struct dpu_soc *dpu)
INIT_LIST_HEAD(&plane_grp->list);
mutex_init(&plane_grp->lock);
plane_grp->id = id / client_num;
plane_grp->has_vproc = display_plane_video_proc;
ret = dpu_get_plane_resource(dpu, &plane_grp->res);
if (ret)

6
include/video/dpu.h
View File

@ -621,7 +621,9 @@ struct dpu_plane_res {
struct dpu_extdst *ed[2];
struct dpu_fetchdecode *fd[MAX_FD_NUM];
struct dpu_framegen *fg;
struct dpu_hscaler *hs[2];
struct dpu_layerblend *lb[MAX_LB_NUM];
struct dpu_vscaler *vs[2];
};
/*
@ -633,13 +635,17 @@ struct dpu_plane_grp {
struct list_head list;
struct mutex lock;
unsigned int hw_plane_num;
unsigned int hw_plane_hscaler_num;
unsigned int hw_plane_vscaler_num;
unsigned int id;
bool has_vproc;
/*
* used when assigning plane source
* index: 0 1 2 3
* source: fd0 fd1 fd2 fd3
*/
u32 src_mask;
u32 src_use_vproc_mask;
};
static inline struct dpu_plane_grp *plane_res_to_grp(struct dpu_plane_res *res)