[TG3]: Add 5709 PHY support.
Add support for the 5709 10/100 PHY. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1035,6 +1035,24 @@ out:
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phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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u32 phy_reg;
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/* adjust output voltage */
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tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
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if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
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u32 phy_reg2;
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tg3_writephy(tp, MII_TG3_EPHY_TEST,
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phy_reg | MII_TG3_EPHY_SHADOW_EN);
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/* Enable auto-MDIX */
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if (!tg3_readphy(tp, 0x10, &phy_reg2))
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tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
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tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
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}
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}
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tg3_phy_set_wirespeed(tp);
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return 0;
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}
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@ -1151,8 +1169,11 @@ static void tg3_power_down_phy(struct tg3 *tp)
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if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
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return;
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tg3_writephy(tp, MII_TG3_EXT_CTRL, MII_TG3_EXT_CTRL_FORCE_LED_OFF);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
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tg3_writephy(tp, MII_TG3_EXT_CTRL,
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MII_TG3_EXT_CTRL_FORCE_LED_OFF);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
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}
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/* The PHY should not be powered down on some chips because
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* of bugs.
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@ -1505,6 +1526,13 @@ static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8
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break;
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default:
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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*speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
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SPEED_10;
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*duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
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DUPLEX_HALF;
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break;
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}
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*speed = SPEED_INVALID;
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*duplex = DUPLEX_INVALID;
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break;
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@ -1787,7 +1815,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
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if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
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tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
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else
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
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tg3_writephy(tp, MII_TG3_IMASK, ~0);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
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@ -6552,7 +6580,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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if (err)
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return err;
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if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
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if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
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u32 tmp;
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/* Clear CRC stats. */
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@ -1624,6 +1624,7 @@
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#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
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#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
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#define MII_TG3_EPHY_PTEST 0x17 /* 5906 PHY register */
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#define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
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@ -1637,6 +1638,8 @@
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#define MII_TG3_AUX_STAT_100FULL 0x0500
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#define MII_TG3_AUX_STAT_1000HALF 0x0600
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#define MII_TG3_AUX_STAT_1000FULL 0x0700
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#define MII_TG3_AUX_STAT_100 0x0008
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#define MII_TG3_AUX_STAT_FULL 0x0001
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#define MII_TG3_ISTAT 0x1a /* IRQ status register */
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#define MII_TG3_IMASK 0x1b /* IRQ mask register */
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@ -1647,6 +1650,9 @@
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#define MII_TG3_INT_DUPLEXCHG 0x0008
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#define MII_TG3_INT_ANEG_PAGE_RX 0x0400
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#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */
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#define MII_TG3_EPHY_SHADOW_EN 0x80
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/* There are two ways to manage the TX descriptors on the tigon3.
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* Either the descriptors are in host DMA'able memory, or they
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* exist only in the cards on-chip SRAM. All 16 send bds are under
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