powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec idle patches. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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@ -1075,6 +1075,8 @@
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#define PVR_8560 0x80200000
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#define PVR_VER_E500V1 0x8020
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#define PVR_VER_E500V2 0x8021
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#define PVR_VER_E6500 0x8040
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/*
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* For the 8xx processors, all of them report the same PVR family for
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* the PowerPC core. The various versions of these processors must be
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@ -171,6 +171,7 @@
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#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
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#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
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#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
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#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */
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#define SPRN_SVR 0x3FF /* System Version Register */
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/*
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@ -217,6 +218,14 @@
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#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
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#define CCR1_TCS 0x00000080 /* Timer Clock Select */
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/* Bit definitions for PWRMGTCR0. */
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#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */
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#define PWRMGTCR0_PW20_ENT_SHIFT 8
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#define PWRMGTCR0_PW20_ENT 0x3F00
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#define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle enable */
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#define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16
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#define PWRMGTCR0_AV_IDLE_CNT 0x3F0000
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/* Bit definitions for the MCSR. */
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#define MCSR_MCS 0x80000000 /* Machine Check Summary */
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#define MCSR_IB 0x40000000 /* Instruction PLB Error */
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