gianfar: Use Single-Queue polling for "fsl,etsec2"
For the "fsl,etsec2" compatible models the driver currently supports 8 Tx and Rx DMA rings (aka HW queues). However, there are only 2 pairs of Rx/Tx interrupt lines, as these controllers are integrated in low power SoCs with 2 CPUs at most. As a result, there are at most 2 NAPI instances that have to service multiple Tx and Rx queues for these devices. This complicates the NAPI polling routine having to iterate over the mutiple Rx/Tx queues hooked to the same interrupt lines. And there's also an overhead at HW level, as the controller needs to service all the 8 Tx rings in a round robin manner. The combined overhead shows up for multi parallel Tx flows transmitted by the kernel stack, when the driver usually starts returning NETDEV_TX_BUSY leading to NETDEV WATCHDOG Tx timeout triggering if the Tx path is congested for too long. As an alternative, this patch makes the driver support only one Tx/Rx DMA ring per NAPI instance (per interrupt group or pair of Tx/Rx interrupt lines) by default. The simplified single queue polling routine (gfar_poll_sq) will be the default napi poll routine for the etsec2 devices too. Some adjustments needed to be made to link the Tx/Rx HW queues with each NAPI instance (2 in this case). The gfar_poll_sq() is already successfully used by older SQ_SG_MODE (single interrupt group) controllers. This patch fixes Tx timeout triggering under heavy Tx traffic load (i.e. iperf -c -P 8) for the "fsl,etsec2" (currently the only MQ_MG_MODE devices). There's also a significant memory footprint reduction by supporting 2 Rx/Tx DMA rings (at most), instead of 8, for these devices. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
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aeb12c5ef7
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@ -363,7 +363,10 @@ static void gfar_mac_rx_config(struct gfar_private *priv)
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if (priv->rx_filer_enable) {
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rctrl |= RCTRL_FILREN;
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/* Program the RIR0 reg with the required distribution */
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gfar_write(®s->rir0, DEFAULT_RIR0);
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if (priv->poll_mode == GFAR_SQ_POLLING)
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gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0);
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else /* GFAR_MQ_POLLING */
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gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0);
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}
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/* Restore PROMISC mode */
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@ -636,7 +639,6 @@ static int gfar_parse_group(struct device_node *np,
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struct gfar_private *priv, const char *model)
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{
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struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
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u32 *queue_mask;
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int i;
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for (i = 0; i < GFAR_NUM_IRQS; i++) {
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@ -665,12 +667,20 @@ static int gfar_parse_group(struct device_node *np,
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grp->priv = priv;
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spin_lock_init(&grp->grplock);
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if (priv->mode == MQ_MG_MODE) {
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queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
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grp->rx_bit_map = queue_mask ?
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*queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
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queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
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grp->tx_bit_map = queue_mask ?
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*queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
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u32 *rxq_mask, *txq_mask;
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rxq_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
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txq_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
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if (priv->poll_mode == GFAR_SQ_POLLING) {
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/* One Q per interrupt group: Q0 to G0, Q1 to G1 */
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grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
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grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
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} else { /* GFAR_MQ_POLLING */
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grp->rx_bit_map = rxq_mask ?
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*rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
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grp->tx_bit_map = txq_mask ?
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*txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
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}
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} else {
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grp->rx_bit_map = 0xFF;
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grp->tx_bit_map = 0xFF;
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@ -686,6 +696,8 @@ static int gfar_parse_group(struct device_node *np,
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* also assign queues to groups
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*/
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for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
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if (!grp->rx_queue)
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grp->rx_queue = priv->rx_queue[i];
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grp->num_rx_queues++;
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grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
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priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
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@ -693,6 +705,8 @@ static int gfar_parse_group(struct device_node *np,
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}
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for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
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if (!grp->tx_queue)
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grp->tx_queue = priv->tx_queue[i];
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grp->num_tx_queues++;
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grp->tstat |= (TSTAT_CLEAR_THALT >> i);
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priv->tqueue |= (TQUEUE_EN0 >> i);
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@ -723,9 +737,22 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
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if (!np || !of_device_is_available(np))
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return -ENODEV;
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/* parse the num of tx and rx queues */
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/* parse the num of HW tx and rx queues */
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tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
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num_tx_qs = tx_queues ? *tx_queues : 1;
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rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
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if (priv->mode == SQ_SG_MODE) {
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num_tx_qs = 1;
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num_rx_qs = 1;
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} else { /* MQ_MG_MODE */
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if (priv->poll_mode == GFAR_SQ_POLLING) {
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num_tx_qs = 2; /* one q per int group */
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num_rx_qs = 2; /* one q per int group */
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} else { /* GFAR_MQ_POLLING */
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num_tx_qs = tx_queues ? *tx_queues : 1;
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num_rx_qs = rx_queues ? *rx_queues : 1;
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}
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}
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if (num_tx_qs > MAX_TX_QS) {
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pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
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@ -734,9 +761,6 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
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return -EINVAL;
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}
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rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
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num_rx_qs = rx_queues ? *rx_queues : 1;
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if (num_rx_qs > MAX_RX_QS) {
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pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
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num_rx_qs, MAX_RX_QS);
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@ -777,6 +801,7 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
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/* Parse and initialize group specific information */
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if (of_device_is_compatible(np, "fsl,etsec2")) {
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priv->mode = MQ_MG_MODE;
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priv->poll_mode = GFAR_SQ_POLLING;
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for_each_child_of_node(np, child) {
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err = gfar_parse_group(child, priv, model);
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if (err)
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@ -784,6 +809,7 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
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}
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} else {
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priv->mode = SQ_SG_MODE;
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priv->poll_mode = GFAR_SQ_POLLING;
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err = gfar_parse_group(np, priv, model);
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if (err)
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goto err_grp_init;
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@ -1263,13 +1289,13 @@ static int gfar_probe(struct platform_device *ofdev)
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dev->ethtool_ops = &gfar_ethtool_ops;
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/* Register for napi ...We are registering NAPI for each grp */
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if (priv->mode == SQ_SG_MODE) {
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netif_napi_add(dev, &priv->gfargrp[0].napi_rx, gfar_poll_rx_sq,
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GFAR_DEV_WEIGHT);
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netif_napi_add(dev, &priv->gfargrp[0].napi_tx, gfar_poll_tx_sq,
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2);
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} else {
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for (i = 0; i < priv->num_grps; i++) {
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for (i = 0; i < priv->num_grps; i++) {
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if (priv->poll_mode == GFAR_SQ_POLLING) {
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netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
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gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
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netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
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gfar_poll_tx_sq, 2);
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} else {
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netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
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gfar_poll_rx, GFAR_DEV_WEIGHT);
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netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
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@ -2819,7 +2845,7 @@ static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
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struct gfar_priv_grp *gfargrp =
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container_of(napi, struct gfar_priv_grp, napi_rx);
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struct gfar __iomem *regs = gfargrp->regs;
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struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0];
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struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
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int work_done = 0;
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/* Clear IEVENT, so interrupts aren't called again
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@ -2850,7 +2876,7 @@ static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
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struct gfar_priv_grp *gfargrp =
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container_of(napi, struct gfar_priv_grp, napi_tx);
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struct gfar __iomem *regs = gfargrp->regs;
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struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0];
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struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
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u32 imask;
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/* Clear IEVENT, so interrupts aren't called again
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@ -412,7 +412,9 @@ extern const char gfar_driver_version[];
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/* This default RIR value directly corresponds
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* to the 3-bit hash value generated */
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#define DEFAULT_RIR0 0x05397700
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#define DEFAULT_8RXQ_RIR0 0x05397700
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/* Map even hash values to Q0, and odd ones to Q1 */
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#define DEFAULT_2RXQ_RIR0 0x04104100
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/* RQFCR register bits */
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#define RQFCR_GPI 0x80000000
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MQ_MG_MODE
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};
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/* GFAR_SQ_POLLING: Single Queue NAPI polling mode
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* The driver supports a single pair of RX/Tx queues
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* per interrupt group (Rx/Tx int line). MQ_MG mode
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* devices have 2 interrupt groups, so the device will
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* have a total of 2 Tx and 2 Rx queues in this case.
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* GFAR_MQ_POLLING: Multi Queue NAPI polling mode
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* The driver supports all the 8 Rx and Tx HW queues
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* each queue mapped by the Device Tree to one of
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* the 2 interrupt groups. This mode implies significant
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* processing overhead (CPU and controller level).
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*/
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enum gfar_poll_mode {
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GFAR_SQ_POLLING = 0,
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GFAR_MQ_POLLING
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};
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/*
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* Per TX queue stats
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*/
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*/
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struct gfar_priv_grp {
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spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES)));
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spinlock_t grplock __aligned(SMP_CACHE_BYTES);
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struct napi_struct napi_rx;
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struct napi_struct napi_tx;
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struct gfar_private *priv;
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struct gfar __iomem *regs;
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unsigned int rstat;
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unsigned long num_rx_queues;
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unsigned long rx_bit_map;
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struct gfar_priv_tx_q *tx_queue;
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struct gfar_priv_rx_q *rx_queue;
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unsigned int tstat;
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unsigned int rstat;
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struct gfar_private *priv;
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unsigned long num_tx_queues;
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unsigned long tx_bit_map;
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unsigned long num_rx_queues;
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unsigned long rx_bit_map;
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struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
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};
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* the buffer descriptor determines the actual condition.
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*/
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struct gfar_private {
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unsigned int num_rx_queues;
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struct device *dev;
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struct net_device *ndev;
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enum gfar_errata errata;
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@ -1065,6 +1084,7 @@ struct gfar_private {
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u16 uses_rxfcb;
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u16 padding;
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u32 device_flags;
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/* HW time stamping enabled flag */
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int hwts_rx_en;
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struct gfar_priv_grp gfargrp[MAXGROUPS];
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unsigned long state;
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u32 device_flags;
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unsigned int mode;
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unsigned short mode;
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unsigned short poll_mode;
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unsigned int num_tx_queues;
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unsigned int num_rx_queues;
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unsigned int num_grps;
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/* Network Statistics */
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