drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from vlv_init_display_clock_gating
On my Cherrytrail CUBE iwork8 Air tablet PIPE-A would get stuck on loading i915 at boot 1 out of every 3 boots, resulting in a non functional LCD. Once the i915 driver has successfully loaded, the panel can be disabled / enabled without hitting this issue. The getting stuck is caused by vlv_init_display_clock_gating() clearing the DPOUNIT_CLOCK_GATE_DISABLE bit in DSPCLK_GATE_D when called from chv_pipe_power_well_ops.enable() on driver load, while a pipe is enabled driving the DSI LCD by the BIOS. Clearing this bit while DSI is in use is a known issue and intel_dsi_pre_enable() / intel_dsi_post_disable() already set / clear it as appropriate. This commit modifies vlv_init_display_clock_gating() to leave the DPOUNIT_CLOCK_GATE_DISABLE bit alone fixing the pipe getting stuck. Changes in v2: -Replace PIPE-A with "a pipe" or "the pipe" in the commit msg and comment Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97330 Cc: stable@vger.kernel.org Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161202142904.25613-1-hdegoede@redhat.com Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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@ -1099,7 +1099,18 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
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static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
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{
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I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
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u32 val;
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/*
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* On driver load, a pipe may be active and driving a DSI display.
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* Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
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* (and never recovering) in this case. intel_dsi_post_disable() will
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* clear it when we turn off the display.
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*/
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val = I915_READ(DSPCLK_GATE_D);
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val &= DPOUNIT_CLOCK_GATE_DISABLE;
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val |= VRHUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(DSPCLK_GATE_D, val);
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/*
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* Disable trickle feed and enable pnd deadline calculation
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