Merge branch 'pci/host-imx6' into next
* pci/host-imx6: PCI: imx6: Fix spelling mistake: "contol" -> "control" PCI: imx6: Do not switch speed if Gen2 is disabled PCI: imx6: Do not wait for speed change on i.MX7 PCI: imx6: Allow probe deferral by reset GPIO PCI: imx6: Add code to support i.MX7D
This commit is contained in:
commit
7284a62dfd
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@ -4,7 +4,11 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie"
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- compatible:
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- "fsl,imx6q-pcie"
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- "fsl,imx6sx-pcie",
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- "fsl,imx6qp-pcie"
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- "fsl,imx7d-pcie"
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- reg: base address and length of the PCIe controller
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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@ -34,6 +38,14 @@ Additional required properties for imx6sx-pcie:
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- clock names: Must include the following additional entries:
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- "pcie_inbound_axi"
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Additional required properties for imx7d-pcie:
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- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
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- resets: Must contain phandles to PCIe-related reset lines exposed by SRC
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IP block
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- reset-names: Must contain the following entires:
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- "pciephy"
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- "apps"
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Example:
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pcie@0x01000000 {
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@ -17,6 +17,7 @@
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
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#include <linux/module.h>
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#include <linux/of_gpio.h>
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#include <linux/of_device.h>
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@ -27,6 +28,7 @@
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#include <linux/signal.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/reset.h>
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#include "pcie-designware.h"
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@ -36,6 +38,7 @@ enum imx6_pcie_variants {
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IMX6Q,
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IMX6SX,
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IMX6QP,
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IMX7D,
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};
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struct imx6_pcie {
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@ -47,6 +50,8 @@ struct imx6_pcie {
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struct clk *pcie_inbound_axi;
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struct clk *pcie;
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struct regmap *iomuxc_gpr;
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struct reset_control *pciephy_reset;
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struct reset_control *apps_reset;
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enum imx6_pcie_variants variant;
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u32 tx_deemph_gen1;
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u32 tx_deemph_gen2_3p5db;
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@ -56,6 +61,11 @@ struct imx6_pcie {
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int link_gen;
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};
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/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
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#define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000
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#define PHY_PLL_LOCK_WAIT_USLEEP_MIN 50
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#define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
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/* PCIe Root Complex registers (memory-mapped) */
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#define PCIE_RC_LCR 0x7c
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#define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
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@ -248,6 +258,10 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
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static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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{
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switch (imx6_pcie->variant) {
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case IMX7D:
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reset_control_assert(imx6_pcie->pciephy_reset);
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reset_control_assert(imx6_pcie->apps_reset);
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break;
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case IMX6SX:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
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@ -303,11 +317,32 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
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break;
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case IMX7D:
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break;
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}
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return ret;
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}
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static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
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{
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u32 val;
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unsigned int retries;
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struct device *dev = imx6_pcie->pci->dev;
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for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; retries++) {
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regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val);
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if (val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED)
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return;
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usleep_range(PHY_PLL_LOCK_WAIT_USLEEP_MIN,
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PHY_PLL_LOCK_WAIT_USLEEP_MAX);
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}
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dev_err(dev, "PCIe PLL lock timeout\n");
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}
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static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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{
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struct dw_pcie *pci = imx6_pcie->pci;
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@ -351,6 +386,10 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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}
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switch (imx6_pcie->variant) {
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case IMX7D:
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reset_control_deassert(imx6_pcie->pciephy_reset);
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imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
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break;
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case IMX6SX:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
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IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
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@ -377,35 +416,44 @@ err_pcie_bus:
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static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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{
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if (imx6_pcie->variant == IMX6SX)
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switch (imx6_pcie->variant) {
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case IMX7D:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
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break;
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case IMX6SX:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6SX_GPR12_PCIE_RX_EQ_MASK,
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IMX6SX_GPR12_PCIE_RX_EQ_2);
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/* FALLTHROUGH */
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default:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
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/* configure constant input signal to the pcie ctrl and phy */
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_DEEMPH_GEN1,
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imx6_pcie->tx_deemph_gen1 << 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
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imx6_pcie->tx_deemph_gen2_3p5db << 6);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
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imx6_pcie->tx_deemph_gen2_6db << 12);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_SWING_FULL,
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imx6_pcie->tx_swing_full << 18);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_SWING_LOW,
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imx6_pcie->tx_swing_low << 25);
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break;
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}
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/* configure constant input signal to the pcie ctrl and phy */
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_DEEMPH_GEN1,
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imx6_pcie->tx_deemph_gen1 << 0);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
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imx6_pcie->tx_deemph_gen2_3p5db << 6);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
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imx6_pcie->tx_deemph_gen2_6db << 12);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_SWING_FULL,
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imx6_pcie->tx_swing_full << 18);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
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IMX6Q_GPR8_TX_SWING_LOW,
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imx6_pcie->tx_swing_low << 25);
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}
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static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
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@ -469,8 +517,11 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
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dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
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/* Start LTSSM. */
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
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if (imx6_pcie->variant == IMX7D)
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reset_control_deassert(imx6_pcie->apps_reset);
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else
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
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ret = imx6_pcie_wait_for_link(imx6_pcie);
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if (ret)
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@ -482,31 +533,42 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
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tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
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tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
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dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
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/*
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* Start Directed Speed Change so the best possible
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* speed both link partners support can be negotiated.
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*/
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tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
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tmp |= PORT_LOGIC_SPEED_CHANGE;
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dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
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if (imx6_pcie->variant != IMX7D) {
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/*
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* On i.MX7, DIRECT_SPEED_CHANGE behaves differently
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* from i.MX6 family when no link speed transition
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* occurs and we go Gen1 -> yep, Gen1. The difference
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* is that, in such case, it will not be cleared by HW
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* which will cause the following code to report false
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* failure.
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*/
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ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
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if (ret) {
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dev_err(dev, "Failed to bring link up!\n");
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goto err_reset_phy;
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}
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}
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/* Make sure link training is finished as well! */
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ret = imx6_pcie_wait_for_link(imx6_pcie);
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if (ret) {
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dev_err(dev, "Failed to bring link up!\n");
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goto err_reset_phy;
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}
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} else {
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dev_info(dev, "Link: Gen2 disabled\n");
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}
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/*
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* Start Directed Speed Change so the best possible speed both link
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* partners support can be negotiated.
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*/
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tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
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tmp |= PORT_LOGIC_SPEED_CHANGE;
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dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
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ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
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if (ret) {
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dev_err(dev, "Failed to bring link up!\n");
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goto err_reset_phy;
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}
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/* Make sure link training is finished as well! */
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ret = imx6_pcie_wait_for_link(imx6_pcie);
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if (ret) {
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dev_err(dev, "Failed to bring link up!\n");
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goto err_reset_phy;
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}
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|
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tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
|
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dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
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return 0;
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|
@ -544,8 +606,8 @@ static struct dw_pcie_host_ops imx6_pcie_host_ops = {
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.host_init = imx6_pcie_host_init,
|
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};
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|
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static int __init imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
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struct platform_device *pdev)
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static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
|
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struct platform_device *pdev)
|
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{
|
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struct dw_pcie *pci = imx6_pcie->pci;
|
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struct pcie_port *pp = &pci->pp;
|
||||
|
@ -585,7 +647,7 @@ static const struct dw_pcie_ops dw_pcie_ops = {
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.link_up = imx6_pcie_link_up,
|
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};
|
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|
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static int __init imx6_pcie_probe(struct platform_device *pdev)
|
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static int imx6_pcie_probe(struct platform_device *pdev)
|
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{
|
||||
struct device *dev = &pdev->dev;
|
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struct dw_pcie *pci;
|
||||
|
@ -609,10 +671,6 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
|
|||
imx6_pcie->variant =
|
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(enum imx6_pcie_variants)of_device_get_match_data(dev);
|
||||
|
||||
/* Added for PCI abort handling */
|
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hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
|
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"imprecise external abort");
|
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|
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dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
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pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
|
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if (IS_ERR(pci->dbi_base))
|
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|
@ -632,6 +690,8 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
|
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dev_err(dev, "unable to get reset gpio\n");
|
||||
return ret;
|
||||
}
|
||||
} else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
|
||||
return imx6_pcie->reset_gpio;
|
||||
}
|
||||
|
||||
/* Fetch clocks */
|
||||
|
@ -653,13 +713,31 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
|
|||
return PTR_ERR(imx6_pcie->pcie);
|
||||
}
|
||||
|
||||
if (imx6_pcie->variant == IMX6SX) {
|
||||
switch (imx6_pcie->variant) {
|
||||
case IMX6SX:
|
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imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
|
||||
"pcie_inbound_axi");
|
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if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
|
||||
dev_err(dev, "pcie_inbound_axi clock missing or invalid\n");
|
||||
return PTR_ERR(imx6_pcie->pcie_inbound_axi);
|
||||
}
|
||||
break;
|
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case IMX7D:
|
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imx6_pcie->pciephy_reset = devm_reset_control_get(dev,
|
||||
"pciephy");
|
||||
if (IS_ERR(imx6_pcie->pciephy_reset)) {
|
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dev_err(dev, "Failed to get PCIEPHY reset control\n");
|
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return PTR_ERR(imx6_pcie->pciephy_reset);
|
||||
}
|
||||
|
||||
imx6_pcie->apps_reset = devm_reset_control_get(dev, "apps");
|
||||
if (IS_ERR(imx6_pcie->apps_reset)) {
|
||||
dev_err(dev, "Failed to get PCIE APPS reset control\n");
|
||||
return PTR_ERR(imx6_pcie->apps_reset);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Grab GPR config register range */
|
||||
|
@ -718,6 +796,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
|
|||
{ .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
|
||||
{ .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
|
||||
{ .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
|
||||
{ .compatible = "fsl,imx7d-pcie", .data = (void *)IMX7D, },
|
||||
{},
|
||||
};
|
||||
|
||||
|
@ -726,11 +805,22 @@ static struct platform_driver imx6_pcie_driver = {
|
|||
.name = "imx6q-pcie",
|
||||
.of_match_table = imx6_pcie_of_match,
|
||||
},
|
||||
.probe = imx6_pcie_probe,
|
||||
.shutdown = imx6_pcie_shutdown,
|
||||
};
|
||||
|
||||
static int __init imx6_pcie_init(void)
|
||||
{
|
||||
return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
|
||||
/*
|
||||
* Since probe() can be deferred we need to make sure that
|
||||
* hook_fault_code is not called after __init memory is freed
|
||||
* by kernel and since imx6q_pcie_abort_handler() is a no-op,
|
||||
* we can install the handler here without risking it
|
||||
* accessing some uninitialized driver state.
|
||||
*/
|
||||
hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
|
||||
"imprecise external abort");
|
||||
|
||||
return platform_driver_register(&imx6_pcie_driver);
|
||||
}
|
||||
device_initcall(imx6_pcie_init);
|
||||
|
|
|
@ -44,4 +44,8 @@
|
|||
|
||||
#define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI (0x1 << 4)
|
||||
|
||||
#define IMX7D_GPR12_PCIE_PHY_REFCLK_SEL BIT(5)
|
||||
|
||||
#define IMX7D_GPR22_PCIE_PHY_PLL_LOCKED BIT(31)
|
||||
|
||||
#endif /* __LINUX_IMX7_IOMUXC_GPR_H */
|
||||
|
|
Loading…
Reference in a new issue