microblaze: Add support for Xilinx PCI host bridge
This patch is based on powerpc patch
64f1650247
We did some cleanups and removed powerpc parts.
There is one new debug early listing function too.
Exclude function is only in Debug options.
We tested in on custom board.
Signed-off-by: Michal Simek <monstr@monstr.eu>
wifi-calibration
Michal Simek
parent
a6475c1322
commit
733cc21831
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@ -267,6 +267,10 @@ config PCI_DOMAINS
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config PCI_SYSCALL
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def_bool PCI
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config PCI_XILINX
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bool "Xilinx PCI host bridge support"
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depends on PCI
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source "drivers/pci/Kconfig"
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endmenu
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@ -166,5 +166,12 @@ extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
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extern void pcibios_setup_bus_devices(struct pci_bus *bus);
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extern void pcibios_setup_bus_self(struct pci_bus *bus);
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/* This part of code was originaly in xilinx-pci.h */
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#ifdef CONFIG_PCI_XILINX
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extern void __init xilinx_pci_init(void);
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#else
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static inline void __init xilinx_pci_init(void) { return; }
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#endif
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#endif /* __KERNEL__ */
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#endif /* __ASM_MICROBLAZE_PCI_H */
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@ -22,6 +22,7 @@
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#include <linux/io.h>
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#include <linux/bug.h>
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#include <linux/param.h>
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#include <linux/pci.h>
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#include <linux/cache.h>
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#include <linux/of_platform.h>
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#include <linux/dma-mapping.h>
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@ -64,6 +65,8 @@ void __init setup_arch(char **cmdline_p)
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setup_memory();
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xilinx_pci_init();
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#if defined(CONFIG_SELFMOD_INTC) || defined(CONFIG_SELFMOD_TIMER)
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printk(KERN_NOTICE "Self modified code enable\n");
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#endif
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@ -3,3 +3,4 @@
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#
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obj-$(CONFIG_PCI) += pci_32.o pci-common.o indirect_pci.o iomap.o
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obj-$(CONFIG_PCI_XILINX) += xilinx_pci.o
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@ -0,0 +1,168 @@
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/*
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* PCI support for Xilinx plbv46_pci soft-core which can be used on
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* Xilinx Virtex ML410 / ML510 boards.
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*
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* Copyright 2009 Roderick Colenbrander
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* Copyright 2009 Secret Lab Technologies Ltd.
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*
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* The pci bridge fixup code was copied from ppc4xx_pci.c and was written
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* by Benjamin Herrenschmidt.
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* Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/ioport.h>
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#include <linux/of.h>
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#include <linux/pci.h>
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#include <asm/io.h>
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#define XPLB_PCI_ADDR 0x10c
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#define XPLB_PCI_DATA 0x110
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#define XPLB_PCI_BUS 0x114
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#define PCI_HOST_ENABLE_CMD (PCI_COMMAND_SERR | PCI_COMMAND_PARITY | \
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)
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static struct of_device_id xilinx_pci_match[] = {
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{ .compatible = "xlnx,plbv46-pci-1.03.a", },
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{}
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};
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/**
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* xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
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*/
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static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
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{
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struct pci_controller *hose;
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int i;
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if (dev->devfn || dev->bus->self)
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return;
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hose = pci_bus_to_host(dev->bus);
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if (!hose)
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return;
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if (!of_match_node(xilinx_pci_match, hose->dn))
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return;
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/* Hide the PCI host BARs from the kernel as their content doesn't
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* fit well in the resource management
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*/
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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dev->resource[i].start = 0;
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dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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}
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dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
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pci_name(dev));
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
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#ifdef DEBUG
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/**
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* xilinx_pci_exclude_device - Don't do config access for non-root bus
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*
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* This is a hack. Config access to any bus other than bus 0 does not
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* currently work on the ML510 so we prevent it here.
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*/
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static int
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xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
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{
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return (bus != 0);
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}
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/**
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* xilinx_early_pci_scan - List pci config space for available devices
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*
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* List pci devices in very early phase.
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*/
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void __init xilinx_early_pci_scan(struct pci_controller *hose)
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{
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u32 bus = 0;
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u32 val, dev, func, offset;
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/* Currently we have only 2 device connected - up-to 32 devices */
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for (dev = 0; dev < 2; dev++) {
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/* List only first function number - up-to 8 functions */
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for (func = 0; func < 1; func++) {
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printk(KERN_INFO "%02x:%02x:%02x", bus, dev, func);
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/* read the first 64 standardized bytes */
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/* Up-to 192 bytes can be list of capabilities */
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for (offset = 0; offset < 64; offset += 4) {
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early_read_config_dword(hose, bus,
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PCI_DEVFN(dev, func), offset, &val);
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if (offset == 0 && val == 0xFFFFFFFF) {
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printk(KERN_CONT "\nABSENT");
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break;
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}
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if (!(offset % 0x10))
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printk(KERN_CONT "\n%04x: ", offset);
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printk(KERN_CONT "%08x ", val);
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}
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printk(KERN_INFO "\n");
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}
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}
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}
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#else
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void __init xilinx_early_pci_scan(struct pci_controller *hose)
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{
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}
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#endif
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/**
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* xilinx_pci_init - Find and register a Xilinx PCI host bridge
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*/
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void __init xilinx_pci_init(void)
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{
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struct pci_controller *hose;
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struct resource r;
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void __iomem *pci_reg;
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struct device_node *pci_node;
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pci_node = of_find_matching_node(NULL, xilinx_pci_match);
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if (!pci_node)
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return;
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if (of_address_to_resource(pci_node, 0, &r)) {
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pr_err("xilinx-pci: cannot resolve base address\n");
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return;
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}
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hose = pcibios_alloc_controller(pci_node);
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if (!hose) {
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pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
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return;
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}
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/* Setup config space */
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setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
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r.start + XPLB_PCI_DATA,
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INDIRECT_TYPE_SET_CFG_TYPE);
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/* According to the xilinx plbv46_pci documentation the soft-core starts
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* a self-init when the bus master enable bit is set. Without this bit
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* set the pci bus can't be scanned.
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*/
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early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
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/* Set the max latency timer to 255 */
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early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
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/* Set the max bus number to 255, and bus/subbus no's to 0 */
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pci_reg = of_iomap(pci_node, 0);
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out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff);
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iounmap(pci_reg);
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/* Register the host bridge with the linux kernel! */
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pci_process_bridge_OF_ranges(hose, pci_node,
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INDIRECT_TYPE_SET_CFG_TYPE);
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pr_info("xilinx-pci: Registered PCI host bridge\n");
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xilinx_early_pci_scan(hose);
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}
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