drm/i915/guc: Keep the ctx_pool_vaddr mapped, for easy access
The GuC descriptor is big in size. If we use a local definition of guc_desc we have a chance to overflow stack, so avoid it. Also, Chris abhors scatterlists :) v2: Rebased, helper function to retrieve the context descriptor, s/ctx_pool_vma/ctx_pool/ v3: Zero out guc_context_desc before initialization v4: Do not do arithmetic on void pointers (Daniele) v5: Nicer than arithmetic on pointers (Chris, Joonas) Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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abddffdf36
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73b055349c
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@ -133,6 +133,13 @@ static int __guc_deallocate_doorbell(struct intel_guc *guc, u32 ctx_index)
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return intel_guc_send(guc, action, ARRAY_SIZE(action));
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}
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static struct guc_context_desc *__get_context_desc(struct i915_guc_client *client)
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{
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struct guc_context_desc *base = client->guc->ctx_pool_vaddr;
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return &base[client->ctx_index];
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}
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/*
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* Initialise, update, or clear doorbell data shared with the GuC
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*
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@ -142,21 +149,11 @@ static int __guc_deallocate_doorbell(struct intel_guc *guc, u32 ctx_index)
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static int __update_doorbell_desc(struct i915_guc_client *client, u16 new_id)
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{
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struct sg_table *sg = client->guc->ctx_pool_vma->pages;
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struct guc_context_desc desc;
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size_t len;
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struct guc_context_desc *desc;
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/* Update the GuC's idea of the doorbell ID */
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len = sg_pcopy_to_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
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sizeof(desc) * client->ctx_index);
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if (len != sizeof(desc))
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return -EFAULT;
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desc.db_id = new_id;
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len = sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
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sizeof(desc) * client->ctx_index);
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if (len != sizeof(desc))
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return -EFAULT;
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desc = __get_context_desc(client);
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desc->db_id = new_id;
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return 0;
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}
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@ -271,29 +268,28 @@ static void guc_proc_desc_init(struct intel_guc *guc,
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* data structures relating to this client (doorbell, process descriptor,
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* write queue, etc).
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*/
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static void guc_ctx_desc_init(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct intel_engine_cs *engine;
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struct i915_gem_context *ctx = client->owner;
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struct guc_context_desc desc;
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struct sg_table *sg;
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struct guc_context_desc *desc;
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unsigned int tmp;
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u32 gfx_addr;
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memset(&desc, 0, sizeof(desc));
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desc = __get_context_desc(client);
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memset(desc, 0, sizeof(*desc));
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desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
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desc.context_id = client->ctx_index;
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desc.priority = client->priority;
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desc.db_id = client->doorbell_id;
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desc->attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
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desc->context_id = client->ctx_index;
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desc->priority = client->priority;
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desc->db_id = client->doorbell_id;
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for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
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struct intel_context *ce = &ctx->engine[engine->id];
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uint32_t guc_engine_id = engine->guc_id;
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struct guc_execlist_context *lrc = &desc.lrc[guc_engine_id];
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struct guc_execlist_context *lrc = &desc->lrc[guc_engine_id];
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/* TODO: We have a design issue to be solved here. Only when we
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* receive the first batch, we know which engine is used by the
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@ -318,49 +314,40 @@ static void guc_ctx_desc_init(struct intel_guc *guc,
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lrc->ring_next_free_location = lrc->ring_begin;
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lrc->ring_current_tail_pointer_value = 0;
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desc.engines_used |= (1 << guc_engine_id);
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desc->engines_used |= (1 << guc_engine_id);
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}
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DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
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client->engines, desc.engines_used);
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WARN_ON(desc.engines_used == 0);
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client->engines, desc->engines_used);
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WARN_ON(desc->engines_used == 0);
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/*
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* The doorbell, process descriptor, and workqueue are all parts
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* of the client object, which the GuC will reference via the GGTT
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*/
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gfx_addr = guc_ggtt_offset(client->vma);
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desc.db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
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desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
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client->doorbell_offset;
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desc.db_trigger_cpu = (uintptr_t)__get_doorbell(client);
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desc.db_trigger_uk = gfx_addr + client->doorbell_offset;
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desc.process_desc = gfx_addr + client->proc_desc_offset;
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desc.wq_addr = gfx_addr + client->wq_offset;
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desc.wq_size = client->wq_size;
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desc->db_trigger_cpu = (uintptr_t)__get_doorbell(client);
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desc->db_trigger_uk = gfx_addr + client->doorbell_offset;
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desc->process_desc = gfx_addr + client->proc_desc_offset;
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desc->wq_addr = gfx_addr + client->wq_offset;
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desc->wq_size = client->wq_size;
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/*
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* XXX: Take LRCs from an existing context if this is not an
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* IsKMDCreatedContext client
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*/
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desc.desc_private = (uintptr_t)client;
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/* Pool context is pinned already */
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sg = guc->ctx_pool_vma->pages;
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sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
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sizeof(desc) * client->ctx_index);
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desc->desc_private = (uintptr_t)client;
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}
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static void guc_ctx_desc_fini(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct guc_context_desc desc;
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struct sg_table *sg;
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struct guc_context_desc *desc;
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memset(&desc, 0, sizeof(desc));
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sg = guc->ctx_pool_vma->pages;
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sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
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sizeof(desc) * client->ctx_index);
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desc = __get_context_desc(client);
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memset(desc, 0, sizeof(*desc));
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}
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/**
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@ -1023,6 +1010,7 @@ int i915_guc_submission_init(struct drm_i915_private *dev_priv)
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const size_t gemsize = round_up(poolsize, PAGE_SIZE);
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struct intel_guc *guc = &dev_priv->guc;
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struct i915_vma *vma;
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void *vaddr;
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if (!HAS_GUC_SCHED(dev_priv))
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return 0;
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@ -1034,14 +1022,21 @@ int i915_guc_submission_init(struct drm_i915_private *dev_priv)
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if (!i915.enable_guc_submission)
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return 0; /* not enabled */
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if (guc->ctx_pool_vma)
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if (guc->ctx_pool)
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return 0; /* already allocated */
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vma = intel_guc_allocate_vma(guc, gemsize);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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guc->ctx_pool_vma = vma;
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guc->ctx_pool = vma;
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vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
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if (IS_ERR(vaddr))
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goto err;
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guc->ctx_pool_vaddr = vaddr;
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ida_init(&guc->ctx_ids);
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intel_guc_log_create(guc);
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guc_addon_create(guc);
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@ -1216,9 +1211,12 @@ void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
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i915_vma_unpin_and_release(&guc->ads_vma);
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i915_vma_unpin_and_release(&guc->log.vma);
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if (guc->ctx_pool_vma)
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if (guc->ctx_pool_vaddr) {
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ida_destroy(&guc->ctx_ids);
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i915_vma_unpin_and_release(&guc->ctx_pool_vma);
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i915_gem_object_unpin_map(guc->ctx_pool->obj);
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}
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i915_vma_unpin_and_release(&guc->ctx_pool);
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}
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/**
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@ -156,7 +156,7 @@ static void guc_params_init(struct drm_i915_private *dev_priv)
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/* If GuC submission is enabled, set up additional parameters here */
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if (i915.enable_guc_submission) {
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u32 pgs = guc_ggtt_offset(dev_priv->guc.ctx_pool_vma);
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u32 pgs = guc_ggtt_offset(dev_priv->guc.ctx_pool);
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u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
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pgs >>= PAGE_SHIFT;
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@ -153,7 +153,8 @@ struct intel_guc {
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bool interrupts_enabled;
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struct i915_vma *ads_vma;
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struct i915_vma *ctx_pool_vma;
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struct i915_vma *ctx_pool;
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void *ctx_pool_vaddr;
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struct ida ctx_ids;
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struct i915_guc_client *execbuf_client;
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