[TG3]: add 5780 fiber support
Add 5780S support by adding a new tg3_setup_fiber_mii_phy() function and a timer function for parallel link detection. 5780S uses standard MII registers for 1000BaseX and runs in GMII mode as opposed to TBI mode on older serdes chips. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1100,7 +1100,7 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
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tp->link_config.orig_autoneg = tp->link_config.autoneg;
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}
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if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
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if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
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tp->link_config.speed = SPEED_10;
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tp->link_config.duplex = DUPLEX_HALF;
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tp->link_config.autoneg = AUTONEG_ENABLE;
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@ -1247,6 +1247,25 @@ static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv
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u32 old_tx_mode = tp->tx_mode;
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if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
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/* Convert 1000BaseX flow control bits to 1000BaseT
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* bits before resolving flow control.
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*/
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if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
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local_adv &= ~(ADVERTISE_PAUSE_CAP |
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ADVERTISE_PAUSE_ASYM);
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remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
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if (local_adv & ADVERTISE_1000XPAUSE)
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local_adv |= ADVERTISE_PAUSE_CAP;
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if (local_adv & ADVERTISE_1000XPSE_ASYM)
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local_adv |= ADVERTISE_PAUSE_ASYM;
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if (remote_adv & LPA_1000XPAUSE)
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remote_adv |= LPA_PAUSE_CAP;
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if (remote_adv & LPA_1000XPAUSE_ASYM)
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remote_adv |= LPA_PAUSE_ASYM;
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}
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if (local_adv & ADVERTISE_PAUSE_CAP) {
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if (local_adv & ADVERTISE_PAUSE_ASYM) {
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if (remote_adv & LPA_PAUSE_CAP)
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@ -2507,12 +2526,226 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
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return 0;
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}
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static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
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{
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int current_link_up, err = 0;
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u32 bmsr, bmcr;
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u16 current_speed;
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u8 current_duplex;
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tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
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tw32_f(MAC_MODE, tp->mac_mode);
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udelay(40);
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tw32(MAC_EVENT, 0);
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tw32_f(MAC_STATUS,
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(MAC_STATUS_SYNC_CHANGED |
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MAC_STATUS_CFG_CHANGED |
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MAC_STATUS_MI_COMPLETION |
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MAC_STATUS_LNKSTATE_CHANGED));
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udelay(40);
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if (force_reset)
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tg3_phy_reset(tp);
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current_link_up = 0;
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current_speed = SPEED_INVALID;
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current_duplex = DUPLEX_INVALID;
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err |= tg3_readphy(tp, MII_BMSR, &bmsr);
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err |= tg3_readphy(tp, MII_BMSR, &bmsr);
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err |= tg3_readphy(tp, MII_BMCR, &bmcr);
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if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
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(tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
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/* do nothing, just check for link up at the end */
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} else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
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u32 adv, new_adv;
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err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
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new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
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ADVERTISE_1000XPAUSE |
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ADVERTISE_1000XPSE_ASYM |
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ADVERTISE_SLCT);
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/* Always advertise symmetric PAUSE just like copper */
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new_adv |= ADVERTISE_1000XPAUSE;
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if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
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new_adv |= ADVERTISE_1000XHALF;
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if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
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new_adv |= ADVERTISE_1000XFULL;
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if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
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tg3_writephy(tp, MII_ADVERTISE, new_adv);
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bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
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tg3_writephy(tp, MII_BMCR, bmcr);
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tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
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tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
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tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
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return err;
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}
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} else {
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u32 new_bmcr;
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bmcr &= ~BMCR_SPEED1000;
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new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
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if (tp->link_config.duplex == DUPLEX_FULL)
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new_bmcr |= BMCR_FULLDPLX;
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if (new_bmcr != bmcr) {
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/* BMCR_SPEED1000 is a reserved bit that needs
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* to be set on write.
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*/
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new_bmcr |= BMCR_SPEED1000;
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/* Force a linkdown */
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if (netif_carrier_ok(tp->dev)) {
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u32 adv;
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err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
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adv &= ~(ADVERTISE_1000XFULL |
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ADVERTISE_1000XHALF |
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ADVERTISE_SLCT);
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tg3_writephy(tp, MII_ADVERTISE, adv);
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tg3_writephy(tp, MII_BMCR, bmcr |
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BMCR_ANRESTART |
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BMCR_ANENABLE);
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udelay(10);
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netif_carrier_off(tp->dev);
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}
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tg3_writephy(tp, MII_BMCR, new_bmcr);
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bmcr = new_bmcr;
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err |= tg3_readphy(tp, MII_BMSR, &bmsr);
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err |= tg3_readphy(tp, MII_BMSR, &bmsr);
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tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
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}
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}
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if (bmsr & BMSR_LSTATUS) {
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current_speed = SPEED_1000;
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current_link_up = 1;
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if (bmcr & BMCR_FULLDPLX)
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current_duplex = DUPLEX_FULL;
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else
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current_duplex = DUPLEX_HALF;
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if (bmcr & BMCR_ANENABLE) {
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u32 local_adv, remote_adv, common;
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err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
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err |= tg3_readphy(tp, MII_LPA, &remote_adv);
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common = local_adv & remote_adv;
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if (common & (ADVERTISE_1000XHALF |
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ADVERTISE_1000XFULL)) {
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if (common & ADVERTISE_1000XFULL)
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current_duplex = DUPLEX_FULL;
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else
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current_duplex = DUPLEX_HALF;
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tg3_setup_flow_control(tp, local_adv,
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remote_adv);
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}
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else
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current_link_up = 0;
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}
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}
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tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
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if (tp->link_config.active_duplex == DUPLEX_HALF)
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tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
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tw32_f(MAC_MODE, tp->mac_mode);
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udelay(40);
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tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
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tp->link_config.active_speed = current_speed;
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tp->link_config.active_duplex = current_duplex;
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if (current_link_up != netif_carrier_ok(tp->dev)) {
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if (current_link_up)
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netif_carrier_on(tp->dev);
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else {
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netif_carrier_off(tp->dev);
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tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
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}
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tg3_link_report(tp);
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}
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return err;
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}
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static void tg3_serdes_parallel_detect(struct tg3 *tp)
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{
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if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
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/* Give autoneg time to complete. */
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tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
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return;
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}
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if (!netif_carrier_ok(tp->dev) &&
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(tp->link_config.autoneg == AUTONEG_ENABLE)) {
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u32 bmcr;
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tg3_readphy(tp, MII_BMCR, &bmcr);
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if (bmcr & BMCR_ANENABLE) {
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u32 phy1, phy2;
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/* Select shadow register 0x1f */
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tg3_writephy(tp, 0x1c, 0x7c00);
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tg3_readphy(tp, 0x1c, &phy1);
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/* Select expansion interrupt status register */
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tg3_writephy(tp, 0x17, 0x0f01);
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tg3_readphy(tp, 0x15, &phy2);
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tg3_readphy(tp, 0x15, &phy2);
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if ((phy1 & 0x10) && !(phy2 & 0x20)) {
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/* We have signal detect and not receiving
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* config code words, link is up by parallel
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* detection.
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*/
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bmcr &= ~BMCR_ANENABLE;
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bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
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tg3_writephy(tp, MII_BMCR, bmcr);
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tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
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}
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}
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}
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else if (netif_carrier_ok(tp->dev) &&
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(tp->link_config.autoneg == AUTONEG_ENABLE) &&
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(tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
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u32 phy2;
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/* Select expansion interrupt status register */
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tg3_writephy(tp, 0x17, 0x0f01);
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tg3_readphy(tp, 0x15, &phy2);
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if (phy2 & 0x20) {
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u32 bmcr;
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/* Config code words received, turn on autoneg. */
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tg3_readphy(tp, MII_BMCR, &bmcr);
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tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
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tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
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}
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}
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}
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static int tg3_setup_phy(struct tg3 *tp, int force_reset)
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{
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int err;
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if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
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err = tg3_setup_fiber_phy(tp, force_reset);
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} else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
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err = tg3_setup_fiber_mii_phy(tp, force_reset);
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} else {
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err = tg3_setup_copper_phy(tp, force_reset);
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}
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@ -4127,6 +4360,9 @@ static int tg3_chip_reset(struct tg3 *tp)
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if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
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tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
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tw32_f(MAC_MODE, tp->mac_mode);
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} else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
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tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
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tw32_f(MAC_MODE, tp->mac_mode);
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} else
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tw32_f(MAC_MODE, 0);
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udelay(40);
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@ -5911,7 +6147,8 @@ static void tg3_timer(unsigned long __opaque)
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udelay(40);
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tg3_setup_phy(tp, 0);
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}
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}
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} else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
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tg3_serdes_parallel_detect(tp);
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tp->timer_counter = tp->timer_multiplier;
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}
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@ -8615,8 +8852,12 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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eeprom_phy_id = 0;
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tp->phy_id = eeprom_phy_id;
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if (eeprom_phy_serdes)
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tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
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if (eeprom_phy_serdes) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
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tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
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else
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tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
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}
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if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
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led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
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@ -8751,7 +8992,7 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
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}
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}
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if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
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if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
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!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
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u32 bmsr, adv_reg, tg3_ctrl;
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@ -8804,7 +9045,7 @@ skip_phy_reset:
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err = tg3_init_5401phy_dsp(tp);
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}
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if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
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if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
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tp->link_config.advertising =
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(ADVERTISED_1000baseT_Half |
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ADVERTISED_1000baseT_Full |
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
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((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
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(tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
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(tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)))
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(tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
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(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
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tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
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if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
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@ -2161,6 +2161,10 @@ struct tg3 {
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#define TG3_FLG2_PROTECTED_NVRAM 0x00100000
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#define TG3_FLG2_USING_MSI 0x00200000
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#define TG3_FLG2_JUMBO_CAPABLE 0x00400000
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#define TG3_FLG2_MII_SERDES 0x00800000
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#define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \
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TG3_FLG2_MII_SERDES)
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#define TG3_FLG2_PARALLEL_DETECT 0x01000000
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u32 split_mode_max_reqs;
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#define SPLIT_MODE_5704_MAX_REQ 3
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